| Title | Thermal-Aware 3D IC Placement Via Transformation |
| Author | Jason Cong, *Guojie Luo, Jie Wei, Yan Zhang (Univ. of California, Los Angeles, United States) |
| Page | pp. 780 - 785 |
| Detailed information (abstract, keywords, etc) | |
| Title | Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling |
| Author | Fayez Mohamood, Michael Healy, Sung Kyu Lim, *Hsien-Hsin S. Lee (Georgia Tech, United States) |
| Page | pp. 786 - 791 |
| Detailed information (abstract, keywords, etc) | |
| Title | On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan Design |
| Author | *Chao-Hung Lu (National Central Univ., Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan), Chien-Nan Jimmy Liu (National Central Univ., Taiwan) |
| Page | pp. 792 - 797 |
| Detailed information (abstract, keywords, etc) | |
| Title | Voltage Island Generation under Performance Requirement for SoC Designs |
| Author | *Wai-Kei Mak, Jr-Wei Chen (National Tsing Hua Univ., Taiwan) |
| Page | pp. 798 - 803 |
| Detailed information (abstract, keywords, etc) | |
| Title | Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign |
| Author | *Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen (National Chiao Tung Univ., Taiwan) |
| Page | pp. 804 - 809 |
| Detailed information (abstract, keywords, etc) | |