| Title | On Reducing Both Shift and Capture Power for Scan-Based Testing |
| Author | Jia Li (Chinese Academy of Sciences, China), *Qiang Xu (The Chinese Univ. of Hong Kong, Hong Kong), Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
| Page | pp. 653 - 658 |
| Keyword | test power, shift power, capture power, scan-based testing |
| Abstract | Power consumption in scan-based testing is a major concern nowadays. In this paper, we present a new X-filling technique to reduce both shift power and capture power during scan tests, namely LSC-filling. The basic idea is to use as few as possible X-bits to keep the capture power under the peak power limit of the circuit under test (CUT), while using the remaining X-bits to reduce the shift power to cut down the CUT’s average power consumption during scan tests as much as possible. In addition, by carefully selecting the X-filling order, our X-filling technique is able to achieve lower capture power when compared to existing methods. Experimental results on ISCAS’89 benchmark circuits show the effectiveness of the proposed methodology. |
| Title | Robust Test Generation for Power Supply Noise Induced Path Delay Faults |
| Author | *Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li (Chinese Academy of Sciences, China) |
| Page | pp. 659 - 662 |
| Keyword | Power Supply Noise, Robust Test generation |
| Abstract | In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS’89 circuits showed test generation can be finished in a few seconds. |
| Title | Test Vector Chains for Increased Targeted and Untargeted Fault Coverage |
| Author | Irith Pomeranz (Purdue University, United States), *Sudhakar M. Reddy (University of Iowa, United States) |
| Page | pp. 663 - 666 |
| Keyword | n-detections, test generation |
| Abstract | We introduce the concept of test vector chains, which allows us to obtain new test vectors from existing ones through single-bit changes without any test generation effort. We demonstrate that a test set T0 has a significant number of test vector chains that are effective in increasing the numbers of detections of target faults, i.e., faults targeted during the generation of T0, as well as untargeted faults, i.e., faults that were not targeted during the generation of T0. |
| Title | Parallel Fault Backtracing for Calculation of Fault Coverage |
| Author | *Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman (Tallinn University of Technology, Estonia) |
| Page | pp. 667 - 672 |
| Keyword | fault simulation, combinational circuits, stuck-at faults, critical path, Boolean differentials |
| Abstract | An improved method for calculation of fault coverage with parallel fault backtracing in digital circuits with scan path is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing. Because of the parallelism and higher abstraction level modeling the speed of analysis was considerably increased. Experimental data show that the speed-up of the new method is considerable compared to the previous similar approach. The speed of the fault analysis in several times outperforms the speed of the current state-of-the-art commercial fault simulators |