Title | An Efficient, Fully Nonlinear, Variability-Aware Non-Monte-Carlo Yield Estimation Procedure with Applications to SRAM Cells and Ring Oscillators |
Author | *Chenjie Gu, Jaijeet Roychowdhury (University of Minnesota, United States) |
Page | pp. 754 - 761 |
Keyword | Yield estimation, non-Monte-Carlo, SRAM, Ring oscillator |
Abstract | Failures and yield problems due to parameter variations have become a significant issue for sub-90-nm technologies. As a result, CAD algorithms and tools that provide designers the ability to estimate the effects of variability quickly and accurately are being urgently sought. The need for such tools is particularly acute for static RAM (SRAM) cells and integrated oscillators, for such circuits require expensive and high-accuracy simulation during design. We present a novel technique for fast computation of parametric yield. The technique is based on efficient, adaptive geometric calculation of probabilistic hypervolumes subtended by the boundary separating pass/fail regions in parameter space. A key feature of the method is that it is far more efficient than Monte-Carlo, while at the same time achieving better accuracy in typical applications. The method works equally well with parameters specified as corners, or with full statistical distributions; importantly, it scales well when many parameters are varied. We apply the method to an SRAM cell and a ring oscillator and provide extensive comparisons against full Monte-Carlo, demonstrating speedups of 100-1000X. |
Title | LTCC Spiral Inductor Modeling, Synthesis, and Optimization |
Author | *Tuck-Boon Chan, Hsin-Chia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen (National Taiwan University, Taiwan) |
Page | pp. 768 - 771 |
Keyword | LTCC, inductor, synthesis, optimization |
Abstract | In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming task due to the tedious try-and-error optimization process. This paper brings forward a fast and accurate spiral inductor synthesis method which automatically generates physical layout of inductors according to electronic specification. The fusion of substrate-aware PEEC model with optimal nonlinear optimization engine, our modeling and synthesis strategies have been extensively verified with 3D solvers and has less than 6% error within measurement result. |
Title | Symmetry Constraint based on Mismatch Analysis for Analog Layout in SOI Technology |
Author | *Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He (Tsinghua University, China), Satoshi Goto (Waseda University, Japan) |
Page | pp. 772 - 775 |
Keyword | mismatch, analog, symmetry, SOI |
Abstract | The conventional tools for mismatch elimination such as geometric symmetry and common centroid technology can only eliminate systematic mismatch, but can do little to reduce random mismatch and thermal-induced mismatch. As the development of VLSI technology, the random mismatch is becoming more and more serious. And in the context of Silicon on Insulator (SOI), the self-heating effect leads to unbearable thermal-induced mismatch. Therefore, in this paper, we first propose a new model which can estimate the combination effect of both random mismatch and thermal-induced mismatch by mismatch analysis and SPICE simulation. And in order to meet the different sensitivities of different symmetry pairs, an automatic classification tool and a configurable optimization process are also introduced. All of these are embedded in the floorplanning process. The final experimental results prove the effectiveness of our method. |