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The 14th Asia and South Pacific Design Automation Conference

Session 6B  Chip and Package Routing Techniques
Time: 15:55 - 18:00 Wednesday, January 21, 2009
Location: Room 413
Chairs: Ting-Chi Wang (National Tsing Hua Univ., Taiwan), Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

6B-1 (Time: 15:55 - 16:20)
TitleEfficient Simulated Evolution Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing
AuthorKe-Ren Dai, *Wen-Hao Liu, Yih-Lang Li (National Chiao Tung Univ., Taiwan)
Pagepp. 570 - 575
Detailed information (abstract, keywords, etc)

6B-2 (Time: 16:20 - 16:45)
TitleFastRoute 4.0: Global Router with Efficient Via Minimization
Author*Yue Xu, Yanheng Zhang, Chris Chu (Iowa State Univ., United States)
Pagepp. 576 - 581
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6B-3s (Time: 16:45 - 16:57)
TitleHigh-Performance Global Routing with Fast Overflow Reduction
Author*Huang-Yu Chen, Chin-Hsiung Hsu, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Pagepp. 582 - 587
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6B-4s (Time: 16:57 - 17:09)
TitleIO Connection Assignment and RDL Routing for Flip-Chip Designs
AuthorJin-Tai Yan, *Zhi-Wei Chen (Chung Hua Univ., Taiwan)
Pagepp. 588 - 593
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6B-5 (Time: 17:09 - 17:34)
TitleOn Using SAT to Ordered Escape Problems
AuthorLijuan Luo, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, United States)
Pagepp. 594 - 599
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6B-6 (Time: 17:34 - 17:59)
TitleA Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound
Author*Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi (Tokyo Inst. of Tech., Japan)
Pagepp. 600 - 605
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