| Title | (Invited Paper) Design Methods for Pipeline & Delta-Sigma A-to-D Converters with Convex Optimization |
| Author | *Kazuo Matsukawa, Takashi Morie, Yusuke Tokunaga, Shiro Sakiyama, Yosuke Mitani, Masao Takayama, Takuji Miki, Akinori Matsumoto, Koji Obata, Shiro Dosho (Panasonic Corp., Japan) |
| Page | pp. 690 - 695 |
| Keyword | optimization, ADC, pipeline, delta, sigma |
| Abstract | In system LSIs, costs of analog circuits are getting increased relatively for rapid cost reduction of digital circuits. To satisfy given specifications in the analog design, including low power and small area, designers have to select an optimal solution among large combination of the following alternatives: which architecture should be adopted; what type of transistors should be taken; and whether digitally assisting technologies should be used or not, etc. A design based on experience and intuition cannot lead to the optimum in a short time. A comprehensive approach to the optimization, based on circuit theory, is now required. Convex optimization procedure can solve the formulae which represent circuit performance with over hundreds of design variables. We have constructed optimization environments for pipelined and delta-sigma analog-to-digital converters (ADCs) in consideration of the digitally assisting techniques and layout constraints. Both 12-bit pipelined ADCs and a 5th-order delta-sigma modulator were designed with the optimizer, and achieved top-ranked power efficiency. |
| Title | (Invited Paper) A Low-Jitter 1.5-GHz and Large-EMI reduction 10-dBm Spread-Spectrum Clock Generator for Serial-ATA |
| Author | *Takashi Kawamoto, Masaru Kokubo (Hitachi, Ltd., Japan) |
| Page | pp. 696 - 701 |
| Keyword | Serial-ATA, PLL, VCO, calibration, SSCG |
| Abstract | A low-jitter and large-EMI-reduction spread spectrum clock generator (SSCG) for Serial-ATA (SATA) was developed. A low-jitter VCO with a high-frequency limiter was developed to prevent SSCGs from malfunctioning. An autocalibration technique suitable for this VCO was developed to prevent SSCGs from degradation because of process variations. A SATA PHY using a technique for calibrating SSCG was developed to use an inexpensive but large frequency-variation reference oscillator. The fabricated SSCG achieved a 10.0-dB EMI reduction and 1.9-3.3 ps rms jitter by the proposed autocalibration technique. The fabricated SATA PHY achieved less than 400-ppm production-frequency tolerance of reference clocks. |