University LSI Design Contest

The University LSI Design Contest was conceived as a unique program of ASP-DAC Conference. The purpose of the Contest is to encourage education and research in LSI design, and its realization on chips at universities, and other educational organizations by providing opportunities to present and discuss innovative and stateof- the-art designs at the conference. Application areas and types of circuits include (1) Analog, RF and Mixed-Signal Circuits, (2) Digital Signal processing, (3) Microprocessors, and (4) Custom Application Specific Circuits and Memories. Methods or technology used for implementation include (a) Full Custom and Cell-Based LSIs, (b) Gate Arrays, and (c) Field Programmable Devices, including FPGA/PLDs. This year, 23 selected designs from five countries/areas will be disclosed in Session 1D with a short presentations followed by live discussions in front of posters with light meals. Submitted designs were reviewed by the members of the University Design Contest Committee. As a result, the 23 designs were selected. Also, we have instituted one outstanding design award and one special feature award.

It is with great pleasure that we acknowledge the contributions to the Design Contest, and it is our earnest belief that it will promote and enhance research and education in LSI design in academic organizations. It is also our hope that many people not only in academia but in industry will attend the contest and enjoy the stimulating discussions.

  • Date: Tuesday, January 20, 2009
  • Place: Pacifico Yokohama, Conference Center, 4F
    • Oral Presentation : Room 416+417 (10:15-12:20)
    • Poster Presentation : Room 418 [Food will be served] (12:20-13:30)
  • Co-chairs : Kazutoshi Kobayashi (Kyoto Univ., Japan), Kenichi Okada (Tokyo Inst. of Technology, Japan)
  • University LSI design contest committee

Award winners

Best Design Award

  • 1D-1 : Shusuke Kawai, Takayuki Ikari, Yutaka Takikawa, Hiroki Ishikuro, Tadahiro Kuroda, "A Wireless Real-Time On-Chip Bus Trace System"

Special Feature Award

  • 1D-13 : Yu-Ting Kuo, Tay-Jyi Lin, Yueh-Tai Li, Chou-Kun Lin, Chih-Wei Liu, "Ultra Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids"
Time Title
1D-1 10:15 - 10:20 A Wireless Real-Time On-Chip Bus Trace System
1D-2 10:20 - 10:25 CKVdd: A Self-Stabilization Ramp-Vdd Technique for Dynamic Power Reduction
1D-3 10:25 - 10:30 A 300 nW, 7 ppm/℃ CMOS Voltage Reference Circuit based on Subthreshold MOSFETs
1D-4 10:30 - 10:35 A 100Mbps, 0.19mW Asynchronous Threshold Detector with DC Power-Free Pulse Discrimination for Impulse UWB Receiver
1D-5 10:35 - 10:40 Low-Power CMOS Transceiver Circuits for 60GHz Band Millimeter-wave Impulse Radio
1D-6 10:40 - 10:45 An Inductor-less MPPT Design for Light Energy Harvesting Systems
1D-7 10:45 - 10:50 A 1 GHz CMOS Comparator with Dynamic Offset Control Technique
1D-8 10:50 - 10:55 Circuit Design Using Stripe-Shaped PMELA TFTs on Glass
1D-9 10:55 - 11:00 Low Energy Level Converter Design for Sub-Vth Logics
1D-10 11:00 - 11:05 A Time-to-Digital Converter with Small Circuitry
1D-11 11:05 - 11:10 A VDD Independent Temperature Sensor Circuit with Scaled CMOS Process
1D-12 11:10 - 11:15 A Current-mode DC-DC Converter using a Quadratic Slope Compensation Scheme
1D-13 11:15 - 11:20 Ultra Low-Power ANSI S1.11 Filter Bank for Digital Hearing Aids
1D-14 11:20 - 11:25 An 11,424 Gate-Count Dynamic Optically Reconfigurable Gate Array with a Photodiode Memory Architecture
1D-15 11:25 - 11:30 A Low-Power FPGA Based on Autonomous Fine-Grain Power-Gating
1D-16 11:30 - 11:35 A 52-mW 8.29mm2 19-mode LDPC Decoder Chip for Mobile WiMAX Applications
1D-17 11:35 - 11:40 A Full-Synthesizable High-Precision Built-In Delay Time Measurement Circuit
1D-18 11:40 - 11:45 A Dynamic Quality-Scalable H.264 Video Encoder Chip
1D-19 11:45 - 11:50 A High Performance LDPC Decoder for IEEE802.11n Standard
1D-20 11:50 - 11:55 Design and Chip Implementation of the Ubiquitous Processor HCgorilla
1D-21 11:55 - 12:00 An 8.69 Mvertices/s 278 Mpixels/s Tile-based 3D Graphics SoC HW/SW Development for Consumer Electronics
1D-22 12:00 - 12:05 A Multi-Task-Oriented Security Processing Architecture with Powerful Extensibility
1D-23 12:05 - 12:10 A Delay-Optimized Universal FPGA Routing Architecture
Last Updated on: 10 30, 2008