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The 15th Asia and South Pacific Design Automation Conference

Session 3A  Emerging Memories and 3D ICs
Time: 8:30 - 10:10 Wednesday, January 20, 2010
Location: Room 101A
Chairs: Mehdi Baradaran Tahoori (Northeastern Univ., U.S.A.), Chin-Long Wey (National Central Univ., Taiwan)

3A-1 (Time: 8:30 - 8:55)
TitleThree-Dimensional Integrated Circuit (3D IC) Floorplan and Power/Ground Network Co-synthesis
AuthorPaul Falkerstern, Yuan Xie (Pennsylvania State Univ., U.S.A.), Yao-Wen Chang (National Taiwan Univ., Taiwan), *Yu Wang (Tsinghua Univ., China)
Pagepp. 169 - 174
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3A-2 (Time: 8:55 - 9:20)
TitlePower and Slew-aware Clock Network Design for Through-Silicon-Via (TSV) Based 3D ICs
Author*Xin Zhao, Sung Kyu Lim (Georgia Tech, U.S.A.)
Pagepp. 175 - 180
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3A-3 (Time: 9:20 - 9:45)
TitleA Novel Si-Tunnel FET based SRAM Design for Ultra Low-Power 0.3V VDD Applications
AuthorJawar Singh (Univ. of Bristol, U.K.), Ramakrishnan Krishnan, Saurabh Mookerjea, Suman Datta, *Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.), Dhiraj Pradhan (Univ. of Bristol, U.K.)
Pagepp. 181 - 186
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3A-4s (Time: 9:45 - 9:57)
TitleCAD Reference Flow for 3D Via-Last Integrated Circuits
Author*Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen-Ching Wu (ITRI, Taiwan)
Pagepp. 187 - 192
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3A-5s (Time: 9:57 - 10:09)
TitleEnergy and Performance Driven Circuit Design for Emerging Phase-Change Memory
AuthorDimin Niu, *Yibo Chen, Xiangyu Dong, Yuan Xie (Pennsylvania State Univ., U.S.A.)
Pagepp. 193 - 198
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