(Back to Session Schedule)

The 15th Asia and South Pacific Design Automation Conference

Session 4C  New Techniques in Technology Mapping
Time: 10:30 - 12:10 Wednesday, January 20, 2010
Location: Room 101C
Chairs: Ting-Ting Hwang (National Tsing Hua Univ., Taiwan), Yuchun Ma (Tsinghua Univ., China)

4C-1 (Time: 10:30 - 10:55)
TitleTechnology Mapping with Crosstalk Noise Avoidance
AuthorFang-Yu Fan (TSMC, Taiwan), *Hung-Ming Chen (NCTU, Taiwan), I-Min Liu (Atoptech, U.S.A.)
Pagepp. 319 - 324
Detailed information (abstract, keywords, etc)
Slides

4C-2 (Time: 10:55 - 11:20)
TitleFault-Tolerant Resynthesis with Dual-Output LUTs
AuthorJu-Yueh Lee (UCLA, U.S.A.), Yu Hu (Univ. of Alberta, Canada), Rupak Majumdar, *Lei He (UCLA, U.S.A.), Minming Li (City Univ. of Hong Kong, Hong Kong)
Pagepp. 325 - 330
Detailed information (abstract, keywords, etc)
Slides

4C-3 (Time: 11:20 - 11:45)
TitleTRECO: Dynamic Technology Remapping for Timing Engineering Change Orders
Author*Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang (National Taiwan Univ., Taiwan)
Pagepp. 331 - 336
Detailed information (abstract, keywords, etc)
Slides

4C-4 (Time: 11:45 - 12:10)
TitleMulti-Operand Adder Synthesis on FPGAs Using Generalized Parallel Counters
Author*Taeko Matsunaga, Shinji Kimura (Waseda Univ., Japan), Yusuke Matsunaga (Kyushu Univ., Japan)
Pagepp. 337 - 342
Detailed information (abstract, keywords, etc)