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The 15th Asia and South Pacific Design Automation Conference

Session 7C  Design Verification and Debugging
Time: 8:30 - 10:10 Thursday, January 21, 2010
Location: Room 101C
Chairs: Yirng-An Chen (Marvell Corp., U.S.A.), Jie-Hong (Roland) Jiang (National Taiwan Univ., Taiwan)

7C-1 (Time: 8:30 - 8:55)
TitleManaging Verification Error Traces with Bounded Model Debugging
Author*Sean Safarpour (Vennsa Technologies, Canada), Andreas Veneris, Farid Najm (Univ. of Toronto, Canada)
Pagepp. 601 - 606
Detailed information (abstract, keywords, etc)
Slides

7C-2 (Time: 8:55 - 9:20)
TitleAutomatic Assertion Extraction via Sequential Data Mining of Simulation Traces
Author*Po-Hsien Chang, Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)
Pagepp. 607 - 612
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7C-3 (Time: 9:20 - 9:45)
TitleAutomatic Constraint Generation for Guided Random Simulation
Author*Hu-Hsi Yeh, Chung-Yang (Ric) Huang (National Taiwan Univ., Taiwan)
Pagepp. 613 - 618
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7C-4 (Time: 9:45 - 10:10)
TitleA Method for Debugging of Pipelined Processors in Formal Verification by Correspondence Checking
Author*Miroslav Velev, Ping Gao (Aries Design Automation, U.S.A.)
Pagepp. 619 - 624
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