| Title | (Invited Paper) Circuit Design Challenges in Embedded Memory and Resistive RAM (RRAM) for Mobile SoC and 3D-IC |
| Author | Meng-Fan Chang (National Tsing Hua University, Taiwan), Pi-Feng Chiu, Shyh-Shyuan Sheu (Industrial Technology Research Institute, Taiwan) |
| Page | pp. 197 - 203 |
| Abstract | Mobile systems require high-performance and low-power SoC or 3D-IC chips to perform complex operations, ensure a small form-factor and ensure a long battery life time. A low supply voltage (VDD) is frequently utilized to suppress dynamic power consumption, standby current, and thermal effects in SoC and 3D-IC. Furthermore, lowering the VDD reduces the voltage stress of the devices and slows the aging of chips. However, a low VDD for embedded memories can cause functional failure and low yield. This paper reviews various challenges in the design of low-voltage circuits for embedded memory (SRAM and ROM). It also discusses emerging embedded memory solutions. Alternative memory interfaces and architectures for mobile SoC and 3D-IC are also explored. |
| Title | (Invited Paper) Emerging Sensing Techniques for Emerging Memories |
| Author | Yiran Chen (University of Pittsburgh, U.S.A.), Hai Li (Polytechnic Institute of New York University, U.S.A.) |
| Page | pp. 204 - 210 |
| Abstract | Among all emerging memories, Spin-Transfer Torque Random Access Memory (STT-RAM) has shown many promising features such as fast access speed, nonvolatility, compatibility to CMOS process and excellent scalability. However, large process variations of both magnetic tunneling junction (MTJ) and MOS transistor severely limit the yield of STT-RAM chips. In this work, we present a recently proposed sensing technique called nondestructive self-reference read scheme (NSRS) to overcome the bit-to-bit variations in STT-RAM by leveraging the different dependencies of the high-resistance state of MTJs on the sensing current biases. Additionally, a few enhancement techniques including R-I curve skewing, yield-driven sensing current selection, and ratio matching are introduced to further improve the robustness of NSRS. The measurements of a 16Kb STT-RAM test chip shows that NSRS can significantly improve the chip yield by reducing sensing failures with high sense margin and low power consumptions. |
| Title | (Invited Paper) A Frequent-Value Based PRAM Memory Architecture |
| Author | Guangyu Sun, Dimin Liu, Jin Ouyang, Yuan Xie (Pennsylvania State University, U.S.A.) |
| Page | pp. 211 - 216 |
| Abstract | Phase Change Random Access Memory (PRAM) has great potential as the replacement of DRAM as main memory, due to its advantages of high density, non-volatility, fast read speed, and excellent scalability. However, poor endurance and high write energy appear to be the challenges to be tackled before PRAM can be adopted as main memory. In order to mitigate these limitations, prior research focuses on reducing write intensity at the bit level. In this work, we study the data pattern of memory write operations, and explore the frequent-value locality in data written back to main memory. Based on the fact that many data are written to memory repeatedly, an architecture of frequent- value storage is proposed for PRAM memory. It can significantly reduce the write intensity to PRAM memory so that the lifetime is improved and the write energy is reduced. The trade-off between endurance and capacity of PRAM memory is explored for different configurations. After using the frequent-value storage, the endurance of PRAM is improved to about 1.6X on average, and the write energy is reduced by 20%. |
| Title | (Invited Paper) Two-Terminal Resistive Switches (Memristors) for Memory and Logic Applications |
| Author | Wei Lu, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba (University of Michigan, U.S.A.) |
| Page | pp. 217 - 223 |
| Abstract | We review the recent progress on the development of two-terminal resistive devices (memristors). Devices based on solid-state electrolytes (e.g. a-Si) have been shown to possess a number of promising performance metrics such as yield, on/off ratio, switching speed, endurance and retention suitable for memory or reconfigurable circuit applications. In addition, devices with incremental resistance changes have been demonstrated and can be used to emulate synaptic functions in hardware based neuromorphic circuits. Device and SPICE modeling based on a properly chosen internal state variable have been carried out and will be useful for large-scale circuit simulations. |