| Title | (Invited Paper) Automatic Formal Verification of Reconfigurable DSPs |
| Author | Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.) |
| Page | pp. 293 - 296 |
| Abstract | We present a method for automatic formal verification of Digital Signal Processors (DSPs) that have VLIW architecture and reconfigurable functional units optimized for accelerating Software Defined Radio (SDR) applications to be used for future space communications by NASA. The formal verification was done with the highly automatic method of Correspondence Checking by exploiting the property of Positive Equality that allows a dramatic simplification of the solution space and many orders of magnitude speedup. The formal verification of a complex reconfigurable DSP took approximately 10 minutes of CPU time on a single workstation, when using our industrial-strength tool flow. |
| Title | (Invited Paper) SoC HW/SW Verification and Validation |
| Author | Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu (National Taiwan University, Taiwan), Thomas B. Huang, Ting-Mao Chang (InPA Systems, Inc., U.S.A.) |
| Page | pp. 297 - 300 |
| Abstract | In modern SoC design flow, verification and validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has impaired its potential strengths in verification and validation. In this paper, we present the technology from InPA Systems in which four different modes of operations, RTL-FPGA co-simulation, SystemC-FPGA co-emulation, vector prototyping, and in-circuit prototyping, are supported. With these different modes of FPGA operations, users can develop and verify their SoCs in different stages of the design flow with different abstraction levels. This methodology efficiently and robustly completes the SoC HW/SW verification and validation flow. |
| Title | (Invited Paper) Utilizing High Level Design Information to Speed up Post-silicon Debugging |
| Author | Masahiro Fujita (The University of Tokyo and CREST, Japan) |
| Page | pp. 301 - 305 |
| Abstract | Due to the highly complicated control structures of modern processors as well as ASICs, some of the logical bugs may easily escape from the pre-silicon verification processes and remain into the silicon. Those bugs can only be found after the chip has been fabricated and used in the systems. So post-silicon debugging is becoming a essential part of the design flows for complicated and large system designs. This paper summarizes our research activities targeting post-silicon debugging for highly complicated pipeline processors as well as large ASICs. We have been working on the following three topics: 1) Translation of chip level error traces to high and abstracted level so that more efficient simulation as well as formal analysis become possible, 2) Utilize experiences on formal verification and debugging processes for pipelined processors for debugging and in-fields rectification of chips, and 3) Apply incremental high level synthesis for efficient in-fields rectifications of ASIC designs. Our approaches utilize high level or abstracted design information as much as possible to make things more efficient and effective. In this paper we briefly present the techniques for the first two topics. |
| Title | (Invited Paper) From RTL to Silicon: The Case for Automated Debug |
| Author | Andreas Veneris, Brian Keng (University of Toronto, Canada), Sean Safarpour (Vennsa Technologies, Inc., Canada) |
| Page | pp. 306 - 310 |
| Abstract | Computer-aided design tools are continuously improving their scalability and efficiency to mitigate the high cost associated with designing and fabricating modern VLSI systems. A key step in the design process is the root-cause analysis of detected errors. Debugging may take months to close, introduce high cost and uncertainty ultimately jeopardizing the chip release date. This study makes the case for debug automation in each part of the design flow (RTL to silicon) to bridge the gap. Contemporary research, challenges and future directions motivate for the urgent need in automation to relieve the pain from this highly manual task. |
| Title | (Invited Paper) Multi-Core Parallel Simulation of System-Level Description Languages |
| Author | Rainer Dömer, Weiwei Chen, Xu Han (University of California, Irvine, U.S.A.), Andreas Gerstlauer (University of Texas at Austin, U.S.A.) |
| Page | pp. 311 - 316 |
| Abstract | The validation of transaction levelmodels described in System-level Description Languages (SLDLs) often relies on extensive simulation. However, traditional Discrete Event (DE) simulation of SLDLs is cooperative and cannot utilize the available parallelism in modern multi-core CPU hosts. In this work, we study the SLDL execution semantics of concurrent threads and present a multi-core parallel simulation approach which automatically protects communication between concurrent threads so that parallel simulation on multi-core hosts becomes possible. We demonstrate significant speed-up in simulation time of several system models, including a H.264 video decoder and a JPEG encoder. |