| Title | Variation-aware Logic Mapping for Crossbar Nano-architectures |
| Author | Masoud Zamani (Northeastern University, U.S.A.), *Mehdi B. Tahoori (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 317 - 322 |
| Keyword | Nano-architectures, Emerging technology, Variation Tolerant, Crossbar Array |
| Abstract | In this paper, we analyze the effect of variations on mapped designs
and propose an efficient mapping method to reduce variation effect
and increase reliability of a circuit implemented on crossbar nanoarchitectures. This method takes advantage of reconfigurability and
abundance of resources in these nano-architectures for tolerating variation and improving reliability. The basic idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation. |
| Title | Routing with Graphene Nanoribbons |
| Author | Tan Yan (Synopsys Inc. & University of Illinois at Urbana-Champaign, U.S.A.), Qiang Ma, Scott Chilstedt, *Martin Wong, Deming Chen (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 323 - 329 |
| Keyword | Routing, Graphene Nanoribbon (GNR), nano-technology |
| Abstract | Conventional CMOS devices are facing an increasing number of challenges as their feature sizes scale down. Graphene nanoribbon (GNR) based devices are shown to be a promising replacement of traditional CMOS at future technology nodes. However, all previous works on GNRs focus at the device level. In order to integrate these devices into electronic systems, routing becomes a key issue. In this paper, the GNR routing problem is studied for the first time. We formulate the GNR routing problem as a minimum hybrid-cost shortest path problem on triangular mesh (“hybrid” means that we need to consider both the length and the bending of the routing path). In order to model this hybrid-cost problem, we apply graph expansion and introduce a shortest red-black path problem on the expanded graph. We then propose an algorithm that solves the shortest red-black path problem optimally. This algorithm is then used in a negotiated congestion based routing scheme. Experimental results show that our GNR routing algorithm effectively handles the hybrid cost. |
| Title | ILP-Based Inter-Die Routing for 3D ICs |
| Author | Chia-Jen Chang, Pao-Jen Huang, *Tai-Chen Chen, Chien-Nan Jimmy Liu (Department of Electrical Engineering, National Central University, Taiwan) |
| Page | pp. 330 - 335 |
| Keyword | 3D-IC, Routing, RDL, Micro-Bump, TSV |
| Abstract | The 3D IC is an emerging technology. The primary emphasis on 3D-IC routing is the interface issues across dies. To handle the interface issue of connections, the inter-die routing, which uses micro bumps and two single-layer RDLs (Re-Distribution Layers) to achieve the connection between adjacent dies, is adopted. In this paper, we present an inter-die routing algorithm for 3D ICs with a pre-defined netlist. Our algorithm is based on integer linear programming (ILP) and adopts a two-stage technique of micro-bump assignment followed by non-regular RDL routing. First, the micro-bump assignment selects suitable micro-bumps for the pre-defined netlist such that no crossing problem exists inside the bounding boxes of each net. After the micro-bump assignment, the netlist is divided into two sub-netlists, one is for the upper RDL and the other is for the lower RDL. Second, the non-regular RDL routing determines minimum and non-crossing global paths for sub-netlists in the upper and lower RDLs individually. Experimental results show that our approach can obtain optimal wirelength and achieve 100% routability under reasonable CPU times. |
| Title | CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits |
| Author | *Shashikanth Bobba (Swiss Institute of Technology Lausanne (EPFL), Switzerland), Ashutosh Chakraborty (University of Texas at Austin, U.S.A.), Olivier Thomas, Perrine Batude, Thomas Ernst, Olivier Faynot (LETI, France), David Z. Pan (University of Texas at Austin, U.S.A.), Giovanni De Micheli (Swiss Institute of Technology Lausanne (EPFL), Switzerland) |
| Page | pp. 336 - 343 |
| Keyword | 3D monolithic integration, CAD tool, Physical design, Placement, Cell design |
| Abstract | 3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is proposed to allow high quality 3-D layout generation. Our experiments demonstrate the effectiveness of CELONCEL technique, fetching us an area gain of 37.5%, 15.51% reduction in wirelength, and 13.49% improvement in overall delay, compared with a 2-D case when benchmarked across an interconnect dominated low-density-parity-check (LDPC) decoder at 45nm technology node. |