| Title | (Invited Paper) Temporal and Spatial Isolation in a Virtualization Layer for Multi-core Processor based Information Appliances |
| Author | Tatsuo Nakajima, Yuki Kinebuchi, Hiromasa Shimada, Alexandre Courbot, Tsung-Han Lin (Waseda University, Japan) |
| Page | pp. 645 - 652 |
| Abstract | A virtualization layer makes it possible to compose multiple functionalities on a multi-core processor with minimum modifications of OS kernels and applications. A multi-core processor is a good candidate to compose various software independently developed for dedicated processors into one multi-core processor to reduce both the hardware and development cost. In this paper, we present SPUMONE, which is a virtualization layer suitable for developing multi-core processor based-information appliances. |
| Title | (Invited Paper) Mathematical Limits of Parallel Computation for Embedded Systems |
| Author | Jason Loew, Jesse Elwell, Dmitry Ponomarev, Patrick H. Madden (SUNY Binghamton Computer Science Department, U.S.A.) |
| Page | pp. 653 - 660 |
| Abstract | Embedded systems are designed to perform a specific set of tasks, and are frequently found in mobile, power constrained environments. There is growing interest in the use of parallel computation as a means to increase performance while reducing power consumption. In this paper, we highlight fundamental limits to what can and cannot be improved by parallel resources. Many of these limitations are easily overlooked, resulting in the design of systems that, rather than improving over prior work, are in fact orders of magnitude worse. |
| Title | (Invited Paper) An Enhanced Leakage-Aware Scheduler for Dynamically Reconfigurable FPGAs |
| Author | Jen-Wei Hsieh (National Taiwan University of Science and Technology, Taiwan), Yuan-Hao Chang (National Taipei University of Technology, Taiwan), Wei-Li Lee (National Taiwan University of Science and Technology, Taiwan) |
| Page | pp. 661 - 667 |
| Abstract | The FPGAs (Field-Programmable Gate Array) are popular in hardware designs and even hardware/software co-designs. Due to the advance of manufacturing technologies, leakage power has become an important issue in the design of modern FPGAs. In particular, the partially dynamical reconfigurable FPGAs allow the latency between FPGA reconfiguration and task execution for the performance consideration. However, this latency introduces unnecessary leakage power called leakage waste. In this work, we propose a leakage-aware scheduling algorithm to minimize the leakage waste without increasing the schedule length of tasks. In this algorithm, a priority dispatcher with a split-aware placement is proposed to reduce the scheduling complexity with considering the hardware constraints of FPGAs. A series of experiments based on synthetic designs demonstrates that the proposed algorithm could effectively reduce leakage waste with limited sacrifices on the task schedulability. |
| Title | (Invited Paper) Power Management Strategies in Data Transmission |
| Author | Tiefei Zhang (Zhejiang University, China), Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo (National Taiwan University, Taiwan), Tianzhou Chen (Zhejiang University, China) |
| Page | pp. 668 - 675 |
| Abstract | With the growing popularity of 3G-powered devices and their serious energy consumption problem, there are growing demands on energy-efficient data transmission strategies for various embedded systems. Different from the past work in energy-efficient real-time task scheduling, we explore strategies to maximize the amount of data transmitted by a 3G module under a given battery capacity. In particular, we present algorithms under different workload configurations with and without timing constraint considerations. Experiments were then conducted to verify the validity of the strategies and develop insights in energy-efficient data transmission. |