NEW!! "Student Group Registration"!!
30% discount for a group of four or more students from the same affiliation(faculty or graduate School) (Applied to Tutorial registration only).

  • Date: Tuesday, January 25, 2011 (9:30 - 17:00)
  • Place: Pacifico Yokohama, Conference Center, 4F
Time Title
Tutorial 1
(Half Day)
9:30 - 12:30 Advanced CMOS Device Technologies (1)
Tutorial 2
(Half Day)
14:00 - 17:00 Advanced CMOS Device Technologies (2)
Tutorial 3
(Half Day)
9:30 - 12:30 3D Integration (1)
Tutorial 4
(Half Day)
14:00 - 17:00 3D Integration (2)
Tutorial 5
(Full Day)
9:30 - 12:30,
14:00 - 17:00
Post Silicon Debug
Tutorial 6
(Full Day)
9:30 - 12:30,
14:00 - 17:00
MPSoC: Multiprocessor System on Chip

Tutorials 1 and 2 (2 Half DAYs)
Tuesday, January 25, 9:30 - 12:30, 14:00 - 17:00 Room 416-417

(Tutorial 1) Advanced CMOS Device Technologies (1)

(Tutorial 2) Advanced CMOS Device Technologies (2)

Ken Uchida (Tokyo Institute of Technology, Japan)
Paul C. McIntyre (Stanford University, USA), Section 1
Shinichi Takagi (The University of Tokyo, Japan), Section 2
Toshiro Hiramoto (The University of Tokyo, Japan), Section 3
Arvind Kumar (IBM, USA), Section 4

Tutorial Summary:

The tutorials are intended to introduce state-of-the-art CMOS device technologies such as High-k/metal-gate, strain-induced performance enhancement, three-dimensional transistor structure technologies. In addition, issues in modern CMOS devices, such as variability of device characteristics, device/circuit co-design, and prospects for future generations will be covered. Each tutorial section will start with the basics of device physics/engineering and end up with discussions on modern, state-of-the-art technologies.

Tutorial Outline:

(Tutorial 1)
Section 1: Gate Stack of Advanced CMOS Devices: High-k/Metal-Gate Technologies
  • Motivation to introduce High-k/Metal-gate
  • History and present status of High-k/Metal-gate research
  • Advanced CMOS devices with High-k/Metal-gate
    • Reliability
    • Variability (Variability of Device, SRAM, Circuit)
  • Remaining issues and prospects of High-k/Metal-gate in 22nm and beyond
(Tutorial 1)
Section 2: Channel/Stress Engineering for Advanced CMOS Devices: Performance Booster Technologies
  • Motivation to introduce stress
  • Effect of stress on device performance
  • Evolution of stress engineering
  • New channel materials (Ge and III-V)
(Tutorial 2)
Section 3: Variability and Device/Circuit Co-Design with Planar Bulk MOSFETs
  • Evolution of advanced CMOS devices
  • Variability (Random dopant)
  • CMOS device/circuit Co-design
    • SRAM in 22nm and beyond
    • Self-repair of SRAM variability
(Tutorial 2)
Section 4: Three-Dimensional Devices for 22nm and Beyond
  • SOI & 3D devices: Ion, Ioff, parasitics
    • Extremely thin SOI devices (ET-SOI)
    • FinFETs
    • Nanowire FETs
  • Circuit design with 3D devices

Tutorials 3 and 4 (2 Half DAYs)
Tuesday, January 25, 9:30 - 12:30, 14:00 - 17:00 Room 414-415

(Tutorial 3) 3D Integration (1)

(Tutorial 4) 3D Integration (2)

Hideki Asai (Shizuoka University, Japan)
Joungho Kim (KAIST, Korea), Section 1
Hideki Asai (Shizuoka University, Japan), Section 2
G. Van der Plas (IMEC, Belgium), Section 3
Erping Li (A-STAR IHPC, Singapore), Section 4

Tutorial Outline:

(Tutorial 3)
Section 1: Signal Integrity of TSV Based 3D IC
Recently, process dimensions of Silicon based semiconductor devices are reaching less than 20 nm scale. However, it suffers significant technical and business challenges including enlarged leakage current and considerable increase of investment budget. As a result, new TSV (Through Silicon Via) based 3D IC technology is emerging as a promising next generation IC technology in both semiconductor industry and academia. In the 3D IC, very thin semiconductor dies of less than 30 um are vertical stacked to minimize the package size and to maximize the semiconductor system performances. In the 3D IC, TSV is becoming the most critical vertical interconnection structure between the semiconductor dies. Around world, most of the semiconductor companies including Intel, IBM, TI, AMD and Qualcomm are seriously considering the TSV based 3D IC as a future direction of the semiconductor integration technology. In the TSV based 3D IC, signal integrity is becoming the major design obstacle due to the high frequency loss, coupling, and electromagnetic radiation, while more than thousand of vertical and lateral interconnections are routed in a tiny 3D space. It could be even more serious in 3D IC for the applications of high-density and multi-function mobile multimedia, computing, and communication system platforms. In this talk, new modeling, measurement, design, and analysis approaches will be introduced in order to enhance the performance and reliability of the 3D IC.
(Tutorial 3)
Section 2: Advanced PI/SI/EMI Simulation Technology for 3D Co-Design
With the progress of system integration technology, a variety of electronic noise problems, so-called power/signal integrity and EMI issues, have become very serious in the field of chip/package/board co-design. Because these noises cause frequently the unexpected behaviors on the today's high-density and high-speed circuits, useful remedies are strongly demanded for the short TAT and cost reduction of high-performance electronic design. In this lecture, the historical overview and the present status of the power/signal integrity issues and electrical simulation technology in the high-speed digital era are described. Furthermore, the future trend, including 3D full-wave and many-core simulation techniques for PI/SI/EMI design, is suggested for the total solution of reliable 3-dimensional co-design.
  • SI/PI/EMI Design Issues
  • Conventional Simulation Techniques
    • Overview and present status
  • Advanced Simulation Techniques
    • High-speed interconnects & planes
  • Future Trend
    • 3D full wave / many core - simulation technology
(Tutorial 4)
Section 3:
3D Cu TSV technology is expected to arrive in products soon. This disruptive integration technology will affect strongly how systems will be designed in the near future. In this tutorial we will briefly introduce the features of the low-cost 3D Cu TSV technology. We will show its performance in terms of 3D interconnect. And how many systems and application can benefit from 3D. Next we will discuss in detail the issues that are important for designers. These include thermal-aware design, ESD, impact of TSV on BEOL and FEOL, reliability of the system, CPI. We will explain how designers can cope with these in early system design (pathfinding flow) and design authoring. The use of “smart samples” to speed up product development in emerging 3D technologies will be explained. Further we will propose a roadmap for based on 3D applications & technology.
(Tutorial 4)
Section 4: Signal integrity and Power Integrity Modeling in high speed electronic integration
Clock frequencies of the high-speed integrated circuits, packages, and systems have increased over the GHz frequency range. The density of transistors per square millimeter greatly increased. More and more circuit modules designed for different purpose share the same piece of silicon in one package, such as the system-on-chip (SOC) and system-on-package (SIP). At the same time, the working frequency becomes higher and higher. The electromagnetic compatibility (EMC) and signal integrity become a very important issue in high speed electronic design. The potential EMC problems should be found and solved as early as possible to reduce the cost on the design-manufacture-test cycle. This talk will introduce the fundamental EMC and signal integrity issues in high-frequency electronic circuits and its packaging. The key EMC problems arising from the high-speed IC& package will be discussed. The current modeling and simulation methods used for IC& package EMC problems will be presented.

Tutorials 5 (Full DAY)
Tuesday, January 25, 9:30 - 12:30, 14:00 - 17:00 Room 413

(Tutorial 5) Post Silicon Debug

Subhasish Mitra (Stanford University, USA)
Rand Gray (Intel, USA)
Nagib Hakim (Intel, USA)
Sascha Junghans (IBM, Germany)

Tutorial Summary:

In this tutorial the processes for debugging chips in a system environment after manufacturing and test are introduced. After an introduction of the scenarios of silicon debug, we present debug methods and strategies for finding logical problems in the design. After this, we will show how electrical problems can be analysed. We conclude with a session on problems and challenges in this area and resulting research topics.

Tutorial Outline:

Section 1: Introduction
  • Design and Verification Process
  • Logical Errors / Electrical errors
Section 2: Logical Errors
  • Pre-Silicon Verificaton
  • Debug strategies for Post-Silicon Validation
  • Checkers and Debug Triggers
  • Analysis of clock running systems
  • Data mining in clock stopped cases
  • Example failures
Section 3: Electrical Errors
  • Sources of problems in both timing and analog circuits
  • Pre-Si verification: Timing convergence and special circuits
  • Examples of on-die circuit marginalities
  • Validation and debug of on-die circuit marginalities
  • Typical causes of analog circuit issues
  • Validation and debug of analog / IO circuits
Section 4: Research Topics
  • Validation test development, Coverage and Risk assessment
  • Observability / survivability hardware structures
  • Debug tools and methodologies (e.g. IFRA/QED)

Tutorials 6 (Full DAY)
Tuesday, January 25, 9:30 - 12:30, 14:00 - 17:00 Room 411-412

(Tutorial 6) MPSoC: Multiprocessor System on Chip

Ahmed Amine Jerraya (CEA-LETI, France)
Takashi Miyamori (Toshiba, Japan), Section 1
Rephael David (LIST, France), Section 2
Sani Nassif (IBM, USA), Section 3
Sungjoo Yoo (Postech, Korea), Section 4

Tutorial Summary:

Today, MPSoC (Multiprocessor system on chip) are deployed in various application domains for building energy efficient computing platforms in advanced process technologies. This has been enabled by a broad range of innovations in hardware architectures, software architectures, programming paradigms and design methods. Different application domains, like computing, multimedia, and wireless communications, pose different requirements. As a result several multicore technologies have emerged and many further research challenges are to be addressed.

As future process technologies will enable further integration, new challenges will arise for defining the (homogeneous and heterogeneous) multicore architectures of future energy efficient computing platforms, employing sophisticated interconnect and memory subsystems. New software architectures and programming paradigms will be needed to use the compute power of the hardware and ease the programming of these platforms. The key challenge will be to make sure that the performance requirements of the targeted applications are met.

This full day tutorial give an in depth overview of state of arts MPSoC HW and SW architectures and outlines future trends.

Tutorial Outline:

Section 1: Energy efficient multicore (MPSoC) architectures
Section 2: Software architecture for energy efficient execution of multicore systems
Section 3: Fabrication technology implications on MPSoC
Section 4: Challenges and trends for MPSoC design especially on memory subsystem and low power consumption
Last Updated on: 10 21, 2010