| Title | JOP-Plus - A Processor for Efficient Execution of Java Programs Extended with GALS Concurrency |
| Author | Muhammad Nadeem, *Morteza Biglari-Abhari, Zoran Salcic (University of Auckland, New Zealand) |
| Page | pp. 17 - 22 |
| Keyword | GALS processor, Java processor, reactivity, concurrency, embedded systems |
| Abstract | In this paper we present an approach to efficiently mix Java with asynchronous and synchronous concurrency and execute it on a specialized Java processor extended with capabilities for concurrency and reactivity. A new processor, which uses JOP (Java Optimized Processor) as its base, executes concurrent programs that comply with Globally Asynchronous Locally Synchronous (GALS) formal model of computation by clearly distinguishing between concurrency and reactivity control flow and Java control flow. The new processor, called JOP-Plus, can be used for embedded and even real-time applications in which majority of code is written in Java and the overall programs specified and structured in SystemJ system-level concurrent programming language. |
| Title | An Application Classification Guided Cache Tuning Heuristic for Multi-core Architectures |
| Author | Marisha Rawlins, *Ann Gordon-Ross (University of Florida, U.S.A.) |
| Page | pp. 23 - 28 |
| Keyword | multi-core, cache tuning, energy, embedded systems |
| Abstract | Since multi-core architectures are becoming more popular, recent multi-core optimizations focus on energy consumption. We present a level one data cache tuning heuristic for a heterogeneous multi-core system, which classifies applications based on data sharing and cache behavior, and uses this classification to guide cache tuning and reduce the number of cores that need to be tuned. Results reveal average energy savings of 25% for 2-, 4-, 8-, and 16-core systems while searching only 1% of the design space. |
| Title | Security Enhanced Linux on Embedded Systems: a Hardware-accelerated Implementation |
| Author | *Leandro Fiorin, Alberto Ferrante, Konstantinos Padarnitas, Francesco Regazzoni (ALaRI, Faculty of Informatics, University of Lugano, Switzerland) |
| Page | pp. 29 - 34 |
| Keyword | Security, SELinux, Embedded Systems, Access Control |
| Abstract | Security Enhanced Linux implements fine-grained mandatory access control. Despite its usefulness, the overhead of implementing it on embedded devices is prohibitive. Therefore, in the past it has been proposed to accelerate SELinux by means of dedicated hardware; in this work we demonstrate the feasibility of such an approach by implementing a hardware accelerator for SELinux on a FPGA-based platform.
Our implementation obtains a huge reduction in the performance overhead and energy consumption of SELinux, yet employing a limited chip area. |
| Title | PRR: A Low-Overhead Cache Replacement Algorithm for Embedded Processors |
| Author | Wei-Che Tseng (University of Texas at Dallas, U.S.A.), *Chun Jason Xue (City University of Hong Kong, Hong Kong), Qingfeng Zhuge, Jingtong Hu, Edwin H.-M. Sha (University of Texas at Dallas, U.S.A.) |
| Page | pp. 35 - 40 |
| Keyword | embedded, cache, replacement, algorithm, round-robin |
| Abstract | In embedded systems power consumption and area tightly constrain the cache capacity and management logic. Many good cache replacement policies have been proposed in the past, but none approach the performance of the least recently used (LRU) algorithm without incurring high overheads. In fact, many embedded designers consider even pseudo-LRU too complex for their embedded systems processors. In this paper, we propose a new level 1 (L1) data cache replacement algorithm, Protected Round-Robin (PRR) that is simple enough to be incorporated into embedded processors while providing miss rates that are very similar to the miss rates of LRU. Our experiments showed that on average the miss rates of PRR are only 0.22 higher than the miss rates of LRU on a 32KB, 4-way L1 data cache with 32 byte long cache lines. PRR has miss rates that are on average 4.72 and 4.66 lower than random and round-robin replacement algorithms, respectively. |