| Title | Thermal-aware Power Network Design for IR Drop Reduction in 3D ICs |
| Author | *Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang (Tsinghua University, China), Tingting Huang (National Tsing Hua University, China), Yuan Xie (Pennsylvania State University, U.S.A.) |
| Page | pp. 47 - 52 |
| Keyword | P/G TSV plan, P/G network, Thermal, 3D ICs |
| Abstract | Due to the high integration on vertical stacked layers, power/ground network design becomes one of the critical challenges in 3D IC design. With the leakage-thermal dependency, the increasing on-chip temperature in 3D designs has serious impact on IR drop due to the increased wire resistance and increased leakage current. Power/ground (P/G) TSVs can help relieve the IR drop violation by vertically connecting the on-chip P/G networks on different layers. However, most previous works only fulfill a margin of the full potential of PG TSVs planning since they restrict P/G grid in a uniform topology. Besides, their overlook of resistance variation and leakage current will make their results less accurate. In this paper, we present an efficient thermal-aware P/G TSVs planning algorithm based on a sensitivity model with temperature-dependent leakage current considered. The proposed method can overcome the limitation of P/G grid topology and make full use of P/G TSVs planning for optimization of P/G network by allowing short wires to connect the P/G TSVs to P/G grids in non-uniform topology. Moreover, with resistance variation and increased leakage current caused by high temperature in 3D ICs, more accurate result can be obtained. Both the theoretical analysis and experimental results show the efficiency of our approach. Results show that neglecting thermal impacts on power delivery can underestimate IR drop by about 11%. To relieve the severe IR drop violation, 51.8% more P/G TSVs are needed than the cases without thermal impacts considered. Results also show that our P/G TSV planning based on the sensitivity model can reduce max IR drop by 42.3% and reduce the number of violated nodes by 82.4%. |
| Title | The Feasibility of Carbon Nanotubes for Power Delivery in 3-D Integrated Circuits |
| Author | *Nauman Khan, Soha Hassoun (Tufts University, U.S.A.) |
| Page | pp. 53 - 58 |
| Keyword | 3-D IC, Through Silicon Via, Power Delivery Network Design, CNT |
| Abstract | Increased power density and package asymmetry
pose challenges in designing power delivery networks for 3-D
Integrated Circuits (ICs). The increased resistivity of Cu wires
due to scaling has shifted attention to alternate interconnect
technologies. Continued and significant innovations in CNT
manufacturing at CMOS-compatible temperatures with quality
low-resistive contacts promise to enable the use of CNT as a
replacement. We investigate in this paper the feasibility of using
CNTs for power delivery in 3-D ICs. We evaluate the use of
CNTs as Through-Silicon Vias (TSVs) and as wiring for global
power delivery grids, fabricated on interposer dies. We assume
the CNT interconnect has a mix of single- and multi-walled
CNTs with 30% metallic nanotubes. We design a 3-D system-level
comparative framework that utilizes select traces from SPEC
benchmarks to evaluate improvements of CNTs over Cu. Our
results emphasize how CNTs can significantly improve power
delivery for 3-D integrated circuits. Using CNTs for on-chip
power grid and for TSVs reduces the number of TSVs by 71%
when compared to a Cu implementation. For the same substrate
area dedicated to power-TSVs, CNTs improve the maximum and
average IR drop by 98% and 40%, respectively. Improvements
in the Ldi/dt drop are 47% and 18%, respectively. |
| Title | An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs |
| Author | *Yi-Ming Wang (Dept. of Electronics Engineering, National Chiao Tung University, Taiwan), Shi-Hao Chen (Global Unichip Corp., Taiwan), Mango C.-T. Chao (Dept. of Electronics Engineering, National Chiao Tung University, Taiwan) |
| Page | pp. 59 - 65 |
| Keyword | power gating, MTCMOS, low power |
| Abstract | MTCMOS is popular in industry for implementing a power gating design. Major IC foundries recommend turning on power switches one by one to reduce the peak current during the mode transition. In this paper, we propose a power-switch-routing framework, which can effectively and efficiently find a feasible Hamiltonian-cycle routing among power switches without violating the Manhattan distance constraint while handling the irregular placement of power switches. The framework is currently used in a design service company. |