| Title | An ILP-based Obstacle-Avoiding Routing Algorithm for Pin-Constrained EWOD Chips |
| Author | *Jia-Wen Chang, Tsung-Wei Huang, Tsung-Yi Ho (National Cheng Kung University, Taiwan) |
| Page | pp. 67 - 72 |
| Keyword | Biochip, ILP, Routing |
| Abstract | Electrowetting-on-dielectric (EWOD) chips, by electrically providing flexible and efficient manipulations of microfluidics, have become the most popular actuator particularly for droplet-based digital microfluidic (DMF) systems. In order to enable the electrical manipulations, wire routing is a key problem in designing EWOD chips. Unlike traditional verylarge-scale-integration (VLSI) routing problems, in addition to routing-path establishment on signal pins, the EWOD-chip routing problem needs to address the issue of signal sharing for pin-count reduction under a practical constraint posed by limited pin-count supply. Moreover, EWOD-chip designs might incur several obstacles in the routing regions due to embedded devices for specific fluidic protocols such as embedded magnets for sample purification and electrophoresis devices for particle separation. However, no existing works consider routing with obstacles. To remedy this insufficiency, we propose in this paper the first obstacle-avoiding routing algorithm for pin-constrained EWOD chips. Our algorithm, based on effective integer-linear-programming (ILP) formulation as well as efficient routing framework, can achieve high routability with a low design complexity. Experimental results based on reallife chips with obstacles demonstrate the high routability of our obstacle-avoiding routing algorithm for pin-constrained EWOD chips. |
| Title | A Look Up Table Design with 3D Bipolar RRAMs |
| Author | Yi-Chung Chen (Polytechnic Institute of New York University, U.S.A.), *Wei Zhang (Nanyang Technological University, Singapore), Hai Li (Polytechnic Institute of New York University, U.S.A.) |
| Page | pp. 73 - 78 |
| Keyword | RRAM, LUT, FPGA, 3D technology |
| Abstract | Look Up Table (LUT) is a basic configurable logic element in Field Programmable Gate Arrays (FPGAs). In commercial product, Static Random Access Memory (SRAM) has been widely used in each LUT to store the configured logic. Recently, the emerging Resistive RAM (RRAM) has attracted a lot of attentions for its high density and non-volatility. In this work, we explore a novel LUT design with bipolar RRAM devices. To obtain design efficiency, a 3D high-density interleaved memory structure is introduced in the proposed LUT. The corresponding peripheral circuits were developed at TSMC 0.18µm technology node. Compared to the traditional SRAM-based FPGA, the RRAM-based LUT demonstrates advantages such as eliminating initialization stage, a much higher density with 56% area reduction, bit-addressable write scheme, dynamic reconfiguration, and the flexibility to support various configurations. |
| Title | Low Power Memristor-Based ReRAM Design with Error Correcting Code |
| Author | *Dimin Niu, Yang Xiao, Yuan Xie (The Pennsylvania State University, U.S.A.) |
| Page | pp. 79 - 84 |
| Keyword | Non-volatile Memory, ReRAM, ECC |
| Abstract | The emerging memristor-based Resistive RAM (ReRAM) has shown great potential as one of the most promising memory technologies, with the unique properties such as high density, low-power, good-scalability, and non-volatility. However, as the process technology scales, the process variation will cause the deviation of the actual electrical behavior of memristor. Recently, researchers have observed that the probability of a single ReRAM cell switching successfully follows a function of the logarithm of the total programming time. As a result, the uncertainty of the electrical behavior results in different degrees of error rates in ReRAM-based memory. Traditional ECC (Error Correcting Code) design for conventional DRAM memory is used to detect and correct the errors in the memory system. In this paper, based on the mathematical analysis of the error patterns in memristor-based ReRAM and the study of ECC designs, we proposed to use ECC code to relax the BER (Bit Error Rate) requirement of a single memory to improve the write energy consumption and latency for both the MOS based and cross point based memristor ReRAM designs. In addition, the performance/power/area overhead of the proposed design options is also evaluated in detail. |
| Title | Synthesis of Reversible Circuits with Minimal Lines for Large Functions |
| Author | Mathias Soeken, *Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler (University of Bremen, Germany) |
| Page | pp. 85 - 92 |
| Keyword | Synthesis, Reversible Logic, Data Structures, QMDDs |
| Abstract | Reversible circuits are an emerging technology where all computations are performed in an invertible manner. Motivated by their promising applications, e.g. in the domain of quantum computation or in the low-power design, the synthesis of such circuits has been intensely studied. However, how to automatically realize reversible circuits with the minimal number of lines for large functions is an open research problem. In this paper, we propose a new synthesis approach which relies on concepts that are complementary to existing ones. While "conventional" function representations have been applied for synthesis so far (such as truth tables, ESOPs, BDDs), we exploit Quantum Multiple-valued Decision Diagrams (QMDDs) for this purpose. An algorithm is presented that performs transformations on this data-structure eventually leading to the desired circuit. Experimental results show the novelty of the proposed approach through enabling automatic synthesis of large reversible functions with the minimal number of circuit lines. Furthermore, the quantum cost of the resulting circuits is reduced by 50% on average compared to an existing state-of-the-art synthesis method. |