| Title | An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology |
| Author | Chia-Ling Chang, Chia-Ching Chang, Hui-Ling Chan, *Charles H.-P. Wen (National Chiao Tung University, Taiwan), Jayanta Bhadra (Freescale Semiconductor Inc., U.S.A.) |
| Page | pp. 163 - 168 |
| Keyword | Iddq testing, data mining |
| Abstract | Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named Sigma-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that Sigma-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently. |
| Title | CODA: A Concurrent Online Delay Measurement Architecture for Critical Paths |
| Author | Yubin Zhang (Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences, China), Haile Yu, *Qiang Xu (The Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 169 - 174 |
| Keyword | online test, delay of critical paths, delay measurement |
| Abstract | With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Correspondingly, various variation-aware and adaptive design methodologies have been proposed. More effective solutions can be obtained if we are able to collect real-time information such as the actual propagation delay of critical paths when the circuit is running in normal function mode. Therefore, we propose novel concurrent online delay measurement architecture for critical paths. Experimental results demonstrate its high accuracy and practicality. |
| Title | Low-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline |
| Author | Mohammad Abdur Rouf, *Soontae Kim (Korea Advanced Institute of Science and Technology, Republic of Korea) |
| Page | pp. 175 - 180 |
| Keyword | Control flow error checking, transient fault, branch target buffer, low energy |
| Abstract | Due to device miniaturization and reducing supply voltage, embedded systems are becoming more susceptible to transient faults. Specifically, faults in control flow can change the execution sequence, which might be catastrophic for safety critical applications. Many techniques are devised using software, hardware or software-hardware co-design for control flow error checking. Software techniques suffer from a significant amount of code size overhead, and hence, negative impact on performance and energy consumption. On the other hand, hardware-based techniques have a significant amount of hardware and area cost. In this research we exploit the available redundancies in the pipeline. The branch target buffer stores target addresses of taken branches, and ALU generates target addresses using the low-order branch displacement bits of branch instructions. To exploit these redundancies in the pipeline, we propose a control flow error checking (CFEC) scheme. It can detect control flow errors and recover from them with negligible energy and performance overhead. |
| Title | Detection and Diagnosis of Faulty Quantum Circuits |
| Author | *Alexandru Paler, Ilia Polian (University of Passau, Germany), John P. Hayes (University of Michigan, U.S.A.) |
| Page | pp. 181 - 186 |
| Keyword | Probabilistic testing, Quantum circuits, Test generation, Fault diagnosis, Design for test |
| Abstract | A new approach to detecting and diagnosing faults in quantum circuits is introduced. In order to account for the probabilistic nature of quantum circuits, collections of test experiments, called binary tomographic tests (BTTs), are generated. A BTT can identify a fault with respect to some userdefined confidence threshold τ. We present an algorithm to generate BTTs that either detect, or ensure the absence of, all modeled faults in a given circuit. We also present an adaptive diagnostic method to locate quantum faults. While classical circuits, even probabilistic ones, only handle ordinary probabilities, quantum circuits deal with quantum states, which have phase as an extra probabilistic parameter. The tomographic testing methods introduced previously for probabilistic circuits are unable to detect differences in phase, and therefore leave many quantum faults undetected. In contrast, we develop a design-for-test method which is specifically intended to detect faults that only affect the phase of a quantum state. We give experimental results for benchmark and random circuits which show high coverage of quantum faults by BTTs, and good resolution in the case of the adaptive diagnosis method. |