| Title | EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation |
| Author | Duo Ding, Bei Yu, Joydeep Ghosh, *David Z. Pan (The University of Texas at Austin, U.S.A.) |
| Page | pp. 263 - 270 |
| Keyword | lithography hotspot detection, meta-classification, high performance, physical verification |
| Abstract | In this paper we present EPIC, a new generic and unified formulation to seamlessly combine the advantages of various types of lithographic hotspot detection techniques. With such formulation, we develop an efficient CAD flow and optimize it with quadratic programming techniques under industry-strength data. After integrating various machine learning and pattern matching detection methods, we evaluate EPIC with a number of industry benchmarks under advanced manufacturing conditions. EPIC demonstrates so far the best capability in selectively combining the desirable features of various hotspot detection methods (3.5-8.2% accuracy improvement) as well as significant suppression of the detection noise (e.g., around 80% false-alarm reduction). These characteristics make EPIC very suitable for conducting high performance physical verification and guiding efficient manufacturability-friendly physical design. |
| Title | GNOMO: Greater-than-NOMinal Vdd Operation for BTI Mitigation |
| Author | *Saket Gupta, Sachin Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 271 - 276 |
| Keyword | Reliability, Mitigation, BTI |
| Abstract | This paper presents a novel scheme for mitigating delay degradations in digital circuits due to bias temperature instability (BTI). The method works in two alternating phases. In the first, a greater-than-nominal supply voltage, Vdd,g is used, which causes a task to complete more quickly but causes greater aging than the nominal supply voltage, Vdd,n. In the second, the circuit is power-gated, enabling the BTI recovery phase. We demonstrate, both at the circuit and the architectural levels, that this approach can significantly mitigate aging for a small performance penalty. |
| Title | Tier-Adaptive-Voltage-Scaling (TAVS): A Methodology for Post-Silicon Tuning of 3D ICs |
| Author | Kwanyeob Chae, *Saibal Mukhopadhyay (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 277 - 282 |
| Keyword | 3D IC, Post-Silicon Tuning, Adaptive-Voltage-Scaling, Variation |
| Abstract | This paper presents tier-adaptive-voltage-scaling (TAVS) as a post-silicon tuning methodology for improving parametric yield of 3D integrated circuits considering die-to-die and within-die process variations. The TAVS methodology senses process corners of individual tiers using on-tier delay sensors and adapt the supply voltage of each tier. The overall TAVS architecture is presented and the circuit issues associated with design of 3D level shifters are discussed. Circuit level simulation and statistical analysis of the TAVS architecture in predictive 45nm technology show the possibility of 26%-39% reduction in chip delay distribution. |
| Title | Body Bias Clustering for Low Test-Cost Post-Silicon Tuning |
| Author | Shuta Kimura, *Masanori Hashimoto, Takao Onoye (Osaka University, Japan) |
| Page | pp. 283 - 289 |
| Keyword | body biasing, body clustering, post-silicon tuning |
| Abstract | Post-silicon tuning is attracting a lot of attention for coping with increasing process variation. However, its tuning cost via testing is still a crucial problem. In this paper, we propose tuningfriendly body bias clustering with multiple bias voltages. The proposed method provides a small set of compensation levels so that the speed and leakage current vary monotonically according to the level. Thanks to this monotonic leveling and limitation of the number of levels, the test-cost of post-silicon tuning is significantly reduced. During the body bias clustering, the proposed method explicitly estimates and minimizes the average leakage after the postsilicon tuning. Experimental results demonstrate that the proposed method reduces the average leakage by 25.3 to 51.9% compared to non clustering case. We reveal that two bias voltages are sufficient when only a small number of compensation levels are allowed for test-cost reduction. We also give an implication on how to synthesize a circuit to which post-silicon tuning will be applied. |