| Title | Block-level 3D IC Design with Through-Silicon-Via Planning |
| Author | Dae Hyun Kim (Georgia Institute of Technology, U.S.A.), Rasit Onur Topaloglu (GLOBALFOUNDRIES, U.S.A.), *Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 335 - 340 |
| Keyword | 3D IC, TSV, 3D RST, Floorplanning |
| Abstract | In this paper, we propose algorithms (finding signal TSV locations, assigning TSVs to whitespace blocks, and manipulating whitespace blocks) for post-floorplanning signal TSV planning in the block-level 3D IC design. Experimental results show that our signal TSV planner outperforms the state-of-the-art TSV-aware 3D floorplanner by 7% to 38% with respect to wirelength. In addition, our multiple TSV insertion algorithm outperforms a single TSV insertion algorithm by 27% to 37%. |
| Title | Micro-Bump Assignment for 3D ICs using Order Relation |
| Author | Ta-Yu Kuan, Yi-Chun Chang, *Tai-Chen Chen (National Central University, Taiwan) |
| Page | pp. 341 - 346 |
| Keyword | 3D ICs, Micro Bump, Placement, RDL, Routing |
| Abstract | The routing quality on RDLs in 3D ICs is affected by the micro-bump location seriously. In this paper, we propose a micro-bump assignment method using order relation to minimize the crossing problem and reduce the detours in RDLs. Experimental results show that our approach can obtain an assignment result with 100% routability and minimal wirelength in global routing. |
| Title | Through-Silicon-Via-Induced Obstacle-Aware Clock Tree Synthesis for 3D ICs |
| Author | Xin Zhao, *Sung Kyu Lim (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 347 - 352 |
| Keyword | TSV, obstacle avoidance, clock synthesis, 3D ICs |
| Abstract | In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that various types of TSVs become obstacles during 3D clock routing including signal, power/ground, and clock TSVs. Some of these TSVs become placement obstacles, i.e., they interfere with clock buffers and clock TSVs; while other TSVs become routing obstacles, i.e., clock wires cannot route through them. Thus, the key is to perform TSV-induced obstacle-aware 3D clock routing under the following goals: (1) clock TSVs and clock buffers are located while avoiding overlap with placement obstacles; (2) clock wires are routed while avoiding routing obstacles; and (3) clock skew and slew constraints are satisfied. Related experiments show that our TSV-obstacle-aware clock tree does not sacrifice wirelength or clock power too much while avoiding various TSV-induced obstacles. |
| Title | Parallel Implementation of R-trees on the GPU |
| Author | Lijuan Luo (University of Illinois at Urbana-Champaign/NVIDIA Corp., U.S.A.), *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Lance Leong (NVIDIA Corp., U.S.A.) |
| Page | pp. 353 - 358 |
| Keyword | R-tree, GPU, parallel programming |
| Abstract | R-tree is an important spatial data structure used in EDA as well as other fields. Although there has been a huge literature of parallel R-tree query, as far as we know, our work is the first successful one to parallelize R-tree query on the GPU. We also propose the first R-tree construction method on the GPU. Unlike the other parallel construction methods, our method does not depend on a partition algorithm and guarantees the same quality as the sequential construction. Experiments show that more than 30x speedup on R-tree query and more than 20x speedup on R-tree construction are achieved. |