| Title | An Adaptive LU Factorization Algorithm for Parallel Circuit Simulation |
| Author | *Xiaoming Chen, Yu Wang, Huazhong Yang (Tsinghua University, China) |
| Page | pp. 359 - 364 |
| Keyword | Parallel LU Factorization, Parallel Circuit Simulation |
| Abstract | Sparse matrix solver has become the bottleneck in SPICE simulator. It is difficult to parallelize the solver
because of the high data-dependency during the numerical LU
factorization. This paper proposes a parallel LU factorization
(with partial pivoting) algorithm on shared-memory computers
with multi-core CPUs, to accelerate circuit simulation. Since
not every matrix is suitable for parallel algorithm, a predictive
method is proposed to decide whether a matrix should use
parallel or sequential algorithm. The experimental results on
35 circuit matrices reveal that the developed algorithm achieves
speedups of 2.11x~8.38x (on geometric-average), compared with
KLU, with 1~8 threads, on the matrices which are suitable
for parallel algorithm. Our solver can be downloaded from
http://nicslu.weebly.com. |
| Title | Predictor-Corrector Latency Insertion Method for Fast Transient Analysis of Ill-Constructed Circuits |
| Author | *Hiroki Kurobe (Graduate School of Eng., Shizuoka University, Japan), Tadatoshi Sekine (Graduate School of Science and Tech., Shizuoka University, Japan), Hideki Asai (Shizuoka University, Japan) |
| Page | pp. 365 - 370 |
| Keyword | coupled multiconductor, fast circuit simulation, high-speed interconnect, latency insertion method, predictor-corrector |
| Abstract | This paper describes a predictor-corrector latency insertion method (LIM) for a fast transient analysis of an ill-constructed circuit. First, the basic LIM algorithm and limitations of the method are described. Next, we propose the predictor-corrector LIM with a large value of fictitious latency for the ill-constructed topologies. Finally, numerical results show that our proposed method is applicable and efficient for the fast simulation of the ill-constructed circuit. |
| Title | Crosstalk-Aware Statistical Interconnect Delay Calculation |
| Author | *Qin Tang, Amir Zjajo, Michel Berkelaar, Nick van der Meijs (Delft University of Technology, Netherlands) |
| Page | pp. 371 - 376 |
| Keyword | crosstalk, interconnect delay, statistical delay calculation, coupling effects, process variations |
| Abstract | As the device geometries are shrinking, the
impact of crosstalk effects increases, which results in a stronger dependence
of interconnect delay on the input arrival time difference between victim and
aggressor inputs (input skew). The increasing process variations
lead to statistical input skew which induces significant interconnect delay variations.
Therefore, it is necessary to take input skew variation
into account for interconnect delay calculation in the presence of
process variations. Existing timing analysis tools evaluate gate and
interconnect delays separately. In this paper, we focus on statistical
interconnect delay calculation considering crosstalk effects.
A piecewise linear delay-change-curve model enables closed-form analytical evaluation of the
statistical interconnect delay caused by input skew (SK) variations.
This method can handle arbitrarily
distributed SK variations.
The process-variation (PV)-induced interconnect delay
variation is handled in a quadratic delay model which considers coupling effects.
The SK- and PV-induced interconnect delay variations are combined together for crosstalk-aware
statistical interconnect delay calculation.
The experimental results indicate that the proposed method can predict the interconnect delay impacted
by both input skew variation and process variations with average (maximum) absolute mean
error 0.25% (0.75%) and standard deviation error 1.31%(3.53%) for different types of
coupled wires in a 65nm technology. |
| Title | Fast Floating Random Walk Algorithm for Multi-Dielectric Capacitance Extraction with Numerical Characterization of Green's Functions |
| Author | Hao Zhuang (Tsinghua University/Peking University, China), *Wenjian Yu, Gang Hu, Zhi Liu, Zuochang Ye (Tsinghua University, China) |
| Page | pp. 377 - 382 |
| Keyword | floating random walk, capacitance extraction, multiple dielectric, thin dielectric, finite difference method |
| Abstract | The floating random walk (FRW) algorithm has several advantages for extracting 3D interconnect capacitance. However, for multi-layer dielectrics in VLSI technology, the efficiency of FRW algorithm would be degraded due to frequent stop of walks at dielectric interface and constraint of first-hop length especially in thin dielectrics. In this paper, we tackle these problems with the numerical characterization of Green's function for cross-interface transition probabilities and weight values. We also present a space management technique with Octree data structure to reduce the time of each hop and parallelize the whole FRW by multi-threaded programming. Numerical results show large speedup brought by the proposed techniques for structures under the VLSI technology with thin dielectric layers. |