| Title | A Multi-Vdd Dynamic Variable-Pipeline On-Chip Router for CMPs |
| Author | *Hiroki Matsutani, Yuto Hirata (Keio University, Japan), Michihiro Koibuchi (National Institute of Informatics, Japan), Kimiyoshi Usami (Shibaura Institute of Technology, Japan), Hiroshi Nakamura (The University of Tokyo, Japan), Hideharu Amano (Keio University, Japan) |
| Page | pp. 407 - 412 |
| Keyword | Network-on-Chip, Low power, Chip multi-processor, Interconnection network |
| Abstract | We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs).
Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload.
Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency is the same for all routers throughout the CMP; thus, there is no need to synchronize neighboring routers working at different frequencies.
In this paper, we implemented the multi-Vdd variable pipeline router, which selects two supply voltage levels and pipeline modes, using a 65nm CMOS process and evaluated it using a full-system CMP simulator.
Evaluation results show that although the application performance degraded by 1.0% to 2.1%, the standby power of NoCs reduced by 10.4% to 44.4%. |
| Title | ARB-NET: A Novel Adaptive Monitoring Platform for Stacked Mesh 3D NoC Architectures |
| Author | *Amir-Mohammad Rahmani, Khalid Latif, Vaddina Kameswar Rao (University of Turku/Turku Centre for Computer Science, Finland), Pasi Liljeberg, Juha Plosila, Hannu Tenhunen (University of Turku, Finland) |
| Page | pp. 413 - 418 |
| Keyword | 3D NoC-Bus Hybrid Architecture, Monitoring Platform, Adaptive Routing Algorithm, 3D ICs |
| Abstract | The emerging three-dimensional integrated circuits (3D ICs) offer a promising solution to mitigate the barriers of interconnect scaling in modern systems. In order to exploit the intrinsic capability of reducing the wire length in 3D ICs, 3D NoC-Bus Hybrid mesh architecture was proposed. Besides its various advantages in terms of area, power consumption, and performance, this architecture has a unique and hitherto previously unexplored way to implement an efficient system-wide monitoring network. In this paper, an integrated low-cost monitoring platform for 3D stacked mesh architectures is proposed which can be efficiently used for various system management purposes. The proposed generic monitoring platform called ARB-NET utilizes bus arbiters to exchange the monitoring information directly with each other without using the data network. As a test case, based on the proposed monitoring platform, a fully congestion-aware adaptive routing algorithm named AdaptiveXYZ is presented taking advantage from viable information generated within bus arbiters. Our extensive simulations with synthetic and real benchmarks reveal that our architecture using the AdaptiveXYZ routing can help achieving significant power and performance improvements compared to recently proposed stacked mesh 3D NoCs. |
| Title | Memory-Aware Mapping and Scheduling of Tasks and Communications on Many-Core SoC |
| Author | *Jinho Lee, Kiyoung Choi (Seoul National University, Republic of Korea) |
| Page | pp. 419 - 424 |
| Keyword | network-on-chip(NoC), mapping, scheduling, QEA, communication type |
| Abstract | This paper presents an approach to automatic task mapping, scheduling, and communication routing on a many-core SoC, considering the trade-offs between two different communication types - message passing and shared memory - for the communication routing in order to optimize the energy consumption or performance. To solve the optimization problem, the approach uses the quantum-inspired evolutionary algorithm. For the scheduling of the tasks with backward dependencies, it uses the iterative modulo scheduling technique. Experiments with random task graphs as well as a set of real applications show the effectiveness of the proposed approach. |