| Title | A Fast Thermal Aware Placement with Accurate Thermal Analysis Based on Green Function |
| Author | Suradeth Aroonsantidecha, *Shih-Ying Liu, Ching-Yu Chin, Hung-Ming Chen (National Chiao Tung University, Taiwan) |
| Page | pp. 425 - 430 |
| Keyword | placement, thermal, Green Function, analytical |
| Abstract | In this paper, we propose a fast and accurate thermal aware analytical placer. Thermal model is constructed based on Green function with enhanced DCT to generate full chip temperature profile. Unlike other previous thermal aware placers, our thermal model is tightly integrated with a flat force directed placement. A thermal spreading force based on 2D Gaussian model is proposed to reduce maximum on-chip temperature with dynamic hot region size control, optimizing between total half-perimeter wirelength (HPWL) and on-chip temperature distribution. |
| Title | Crosstalk-Aware Power Optimization with Multi-Bit Flip-Flops |
| Author | *Chih-Cheng Hsu, Yao-Tsung Chang, Mark Po-Hung Lin (National Chung Cheng University, Taiwan) |
| Page | pp. 431 - 436 |
| Keyword | power optimization, crosstalk, synthesis for low power, physical design, multi-bit flip-flop |
| Abstract | Applying multi-bit flip-flops (MBFFs) for clock power reduction in modern nanometer ICs has been becoming a promising lower-power design technique. Many previous works tried to utilize as more MBFFs with larger bit numbers as possible to gain more clock power saving. However, an MBFF with a larger bit number may lead to serious crosstalk due to the close interconnecting wires belonging to different signal nets which are connected to the same MBFF. To address the problem, this paper analyzes, evaluates, and compares the relationship between power consumption and crosstalk when applying MBFFs with different bit numbers. To solve the addressed problem, a novel crosstalk-aware power optimization approach is further proposed to optimize power consumption while satisfying the crosstalk constraint. Experimental results show that the proposed approach is very effective in crosstalk avoidance when applying MBFFs for power optimization. To our best knowledge, this is also the first work in the literature that considers the crosstalk effect for the MBFF application. |
| Title | Topology-Aware Buffer Insertion and GPU-Based Massively Parallel Rerouting for ECO Timing Optimization |
| Author | *Yen-Hung Lin, Yun-Jian Lo, Jian-Syun Tong, Wen-Hao Liu, Yih-Lang Li (National Chiao Tung University, Taiwan) |
| Page | pp. 437 - 442 |
| Keyword | Topology, Timing ECO, Rotuing, Parallel EDA, GPU |
| Abstract | Conventional buffer insertion in timing ECO involves only mini-mizing the arrival time of the most critical sink in one multi-pin net and neglects the obstacles and the topology of routed wire segments, which may worsen the arrival times of other sinks and burden subsequent timing ECO. This work develops a topology-aware ECO timing optimization (TOPO) flow that comprises three phases - buffering pair scoring, edge breaking and buffer connection, and topol-ogy restructuring. TOPO effectively improves the arrival times of violation sinks without worsening those of other sinks. Experimental results indicate that TOPO improves the worst negative slack (WNS) and total negative slack (TNS) of benchmarks by an average of 79.2% and 84.3%, respectively. The proposed algorithm improves the arrival time that is achieved using conventional two-pin net-based buffer insertion by an average of 40.4%, at the cost of consuming 19× runtime. To speed up routing and further improve sink slack, a highly scalable massively parallel maze routing on Graphics Processing Unit (GPU) platform is also developed to enable the proposed flow to explore more solution candidates. High scalability and parallelism are realized by block partitioning and staggering. Experiments reveal that the proposed GPU-based parallel maze routing can achieve near 12× runtime speedup for two-pin routings. With parallelized maze routing, WNS violations in four out of five cases can be resolved. |
| Title | Voltage Island-Driven Floorplanning Considering Level Shifter Placement |
| Author | Richard C.J. Hsu, Wei-Yi Cheng, Chung-Lin Lee, *Jai-Ming Lin (National Cheng Kung University, Taiwan) |
| Page | pp. 443 - 448 |
| Keyword | multiple-supply voltage (MSV), level-shifter, floorplanning/placement, Low power, physical design |
| Abstract | Low power has become a burning issue in modern VLSI design. To deal with this problem, the multiple-supply voltage (MSV) is a technique widely applied to a design to reduce its power consumption. However, there exist several challenges in implementing Multi-Voltage designs, which includes floorplanning, level-shifter placement, and power planning. Among these challenges, placement of level shifters has direct impacts on the chip area, total wirelength, and power planning. Although several works considering MSV driven floorplanning have been proposed, they do not actually place level shifters in their flows, which makes their results unrealistic. Yu et al. first proposed a methodology to place level shifters during floorplanning. But, level shifters are inserted in the whitespace of a chip, which would increase wirelength of long wires and make power planning more difficult. Thus, in this paper, we first propose two ways to allocate regions for level shifters during floorplanning, and then give a two-stage approach to place these level shifters at proper locations. The experimental results reveal that the wirelength is underestimated if we do place level shifters and it can obtain smaller wirelength if we can consider level shifters during floorplanning. |