| Title | A Semi-Formal Min-Cost Buffer Insertion Technique Considering Multi-Mode Multi-Corner Timing Constraints |
| Author | *Shih Heng Tsai, Man Yu Li, Chung Yang Huang (GIEE, National Taiwan University, Taiwan) |
| Page | pp. 505 - 510 |
| Keyword | Buffer insertion, optimization |
| Abstract | Buffer Insertion has always been the most effective approach for timing optimization in VLSI designs. However, the emerging low-power design paradigm and the consideration of multiple operation modes and process corners (MMMC) have raised great challenges. Traditional dynamic-programming-based techniques are unable to cope with these challenges. In this paper, we develop a novel buffer insertion algorithm that utilizes a neighborhood restriction to simplify the constraint formulation and applies a semi-formal buffer refinement process to minimize buffer cost. The experimental results show that our tool can significantly reduce the buffer cost while meeting the MMMC timing constraints. |
| Title | ECO Timing Optimization with Negotiation-Based Re-Routing and Logic Re-Structuring Using Spare Cells |
| Author | Xing Wei, *Wai-Chung Tang, Yi Diao, Yu-Liang Wu (Chinese University of Hong Kong, Hong Kong) |
| Page | pp. 511 - 516 |
| Keyword | ECO, Timing Optimization, Negotiation-based Routing, Logic Rewiring |
| Abstract | To maintain a lower re-masking cost, Engineering Change Order (ECO) using pre-placed spare cells for buffer insertion and gate sizing has been shown to be practical for fixing timing violating paths (ECO paths). However, in the previously known best scheme DCP, re-routings are done with each path optimized according to its surrounding available spare cells without considering potential exchanges with neighboring active cells, and spare cell arbitration between competing ECO paths are less addressed. Besides, the extra flexibility for allowing logic restructuring was not exploited. In this work, we develop a framework harnessing the following more flexible strategies to make the usage of spare cells for ECO timing optimization more powerful: (1) a negotiation based re-routing scheme yielding a more global view in solving resource competition arbitration; (2) an extended gate sizing operation to allow exchanges of active gates with spare gates of different function types through equivalent logic re-structuring. Our experiments upon MCNC and ITC benchmarks with highly injected timing violations show that compared to DCP, our newly proposed framework can cut down the average total negative slack (TNS) by 50% and reduce the number of unsolved ECO paths by 31%. |
| Title | Clock Rescheduling for Timing Engineering Change Orders |
| Author | *Kuan-Hsien Ho, Xin-Wei Shih, Jie-Hong R. Jiang (National Taiwan University, Taiwan) |
| Page | pp. 517 - 522 |
| Keyword | Timing ECO, Clock Rescheduling, Spare Cells, Gate Sizing, Buffer Insertion |
| Abstract | With increasing circuit complexities, design bugs are commonly found in late design stages, and thus engineering change orders (ECOs) have become an indispensable process in modern designs. Most prior approaches to the timing ECO problem are concerned about combinational logic optimization. In contrast, this paper addresses the problem in the sequential domain to explore more optimization flexibility. Experimental results based on five industrial designs show the effectiveness of our work. Our framework has been integrated into a commercial design flow. |
| Title | Optimal Prescribed-Domain Clock Skew Scheduling |
| Author | Li Li, Yinghai Lu, *Hai Zhou (Northwestern University, U.S.A.) |
| Page | pp. 523 - 527 |
| Keyword | prescribed-domain, clock skew scheduling, optimal |
| Abstract | Clock skew scheduling is an efficient technique to minimize the cycle
period by properly assigning clock delays to registers in a
circuit. But its effectiveness is limited by the difficulty
in implementing a large number of arbitrary clock skews. Multi-domain clock skew
scheduling and prescribed-domain clock skew scheduling
are two alternatives to overcome this shortage by restricting the number of clock domains. While multi-domain
clock skew scheduling has been proved to be NP-hard, the hardness of prescribed-domain clock skew scheduling algorithm
remains evasive. In this paper, we give a positive answer to the open question by
presenting the first efficient and optimal algorithm for
prescribed-domain clock skew scheduling. Besides the runtime improvement
over the previous method, the experimental results on ISCAS89 benchmarks show
comparable quality to those generated by optimal multi-domain
clock skew scheduling. |