| Title | Fast Simulation of Hybrid CMOS and STT-MTJ Circuits with Identified Internal State Variables |
| Author | Yang Shang, Wei Fei, *Hao Yu (Nanyang Technological University, Singapore) |
| Page | pp. 529 - 534 |
| Keyword | STT-MTJ, Internal State Variable, Fast simulation |
| Abstract | Hybrid integration of CMOS and non-volatile memory (NVM) devices has become the technology foundation for emerging non-volatile memory based computing. The primary challenge to validate a hybrid system with both CMOS and non-volatile devices is to develop a SPICE-like simulator that can simulate the dynamic behavior of hybrid system accurately and efficiently. Since spin-transfer-toque magnetic-tunneling-junction (STT-MTJ) device is one of the most promising candidates of next generation NVM devices, it is under great interest in including this new device in the standard CMOS design flow. The previous approaches require complex equivalent circuits to represent the STT-MTJ device, and ignore dynamic effect without consideration of internal states. This paper proposes a new modified nodal analysis for STT-MTJ device with identified internal state variables. As demonstrated by a number of experiment examples on hybrid systems with both CMOS and STT-MTJ devices, our newly developed SPICE-like simulator can deal with the dynamic behavior of STT-MTJ device under arbitrary driving condition and reduce the CPU time by more than 20 times for memory circuits when compared to the previous equivalent circuit approaches. |
| Title | Time-Domain Performance Bound Analysis of Analog Circuits Considering Process Variations |
| Author | Xue-Xin Liu, *Sheldon X.-D. Tan, Zhigang Hao (University of California, Riverside, U.S.A.), Guoyong Shi (Shanghai Jiao Tong University, China) |
| Page | pp. 535 - 540 |
| Keyword | performance bound, time domain, interval, process variation |
| Abstract | In this paper, we propose a new time-domain performance bound analysis method for analog circuits with process variations. The proposed method, called TIDBA, consists of several steps to compute the bound performances in time domain. First the performance bound in frequency domain is computed for a linearized analog circuits by an variational symbolic analysis method and the Kharitonov's functions. Then the time domain performance bound is computed via a new general-signal transient bound analysis using FFT/IFFT. The new algorithm can give correctly lower bound and upper bound of the performance variations of analog circuits accurately and reliably. Experimental results from two industry benchmark circuits show that TIDBA gives the correct bounds for the Monte Carlo analysis while it delivers one order of magnitude speedup over the Monte Carlo method. |
| Title | Hierarchical Graph Reduction Approach to Symbolic Circuit Analysis with Data Sharing and Cancellation-Free Properties |
| Author | Yang Song, *Guoyong Shi (Shanghai Jiao Tong University, China) |
| Page | pp. 541 - 546 |
| Keyword | analog IC, BDD, cancellation-free, graph reduction, hierarchical analysis |
| Abstract | Parallel to algebraic methods, graphical circuit analysis methods have the advantage of
cancellation-free. This paper proposes a graph reduction method for hierarchical
symbolic circuit analysis by applying a binary decision diagram (BDD) for data sharing.
This method is extended from the Graph-Pair Decision Diagram (GPDD) method which was
developed for two-port dependent sources. New graph construction rules for multiple-port
dependent sources are introduced, with which large analog circuits can be analyzed
hierarchically. The new hierarchical method guarantees the \emph{cancellation-free}
property at each layer of hierarchy. The BDD-based hierarchical analysis method
can greatly reduce the analysis complexity of the entire circuit, while the software
construction and circuit partition remain easy. The new method is compared to
the algebraic hierarchical method based on DDD (Determinant Decision Diagram) which
does not have the cancellation-free property. Comparable performance can be achieved
with the new method which has the extra cancellation-free property. |
| Title | Weakly Nonlinear Circuit Analysis Based on Fast Multidimensional Inverse Laplace Transform |
| Author | *Tingting Wang, Haotian Liu, Yuanzhe Wang, Ngai Wong (The University of Hong Kong, Hong Kong) |
| Page | pp. 547 - 552 |
| Keyword | Numerical inverse Laplace transform, Laguerre functions, parallel computing, nonlinear circuit, Volterra series |
| Abstract | There have been continuing thrusts in developing efficient modeling techniques for circuit simulation. However, most circuit simulation methods are time-domain solvers. In this paper we propose a frequency-domain simulation method based on Laguerre function expansion. The proposed method handles both linear and nonlinear circuits. The Laguerre method can invert multidimensional Laplace transform efficiently with a high accuracy, which is a key step of the proposed method. Besides, an adaptive mesh refinement (AMR) technique is developed and its parallel implementation is introduced to speed up the computation. Numerical examples show that our proposed method can accurately simulate large circuits while enjoying low computation complexity. |