| Title | Automatic Timing Granularity Adjustment for Host-Compiled Software Simulation |
| Author | Parisa Razaghi, *Andreas Gerstlauer (The University of Texas at Austin, U.S.A.) |
| Page | pp. 567 - 572 |
| Keyword | Real-time systems, host-compiled simulation, Abstract RTOS modeling |
| Abstract | Host-compiled simulation has been widely adopted as a practical approach for fast and high-level evaluation of complex software-intensive systems at early stages of the design process. In such approaches, higher speed is achieved by coarse-grained simulation of the system, which also leads to a loss in timing accuracy. To eliminate the inherent speed and accuracy tradeoff, we present an adjustive software simulator, which automatically controls the timing model of the simulation platform to provide both fast and accurate results. At its core, we propose a novel RTOS model that permanently monitors the state of the system and optimally and automatically adjusts back-annotated timing granularities to provide an error-free task scheduling. We evaluated our approach on an industrial-strength example, and results show that the accuracy of a fine-grain simulation can be achieved while maintaining a speed of close to 900MIPS. |
| Title | Performance Estimation of Embedded Software with Confidence Levels |
| Author | *Marco Lattuada, Fabrizio Ferrandi (Politecnico di Milano, Italy) |
| Page | pp. 573 - 578 |
| Keyword | Performance Estimation, Prediction Intervals, Confidence Levels |
| Abstract | Since time constraints are a very critical aspect of an embedded system, performance evaluation can not be postponed to the end of the design flow, but it has to be introduced since its early stages.
Estimation techniques based on mathematical models are usually preferred during this phase since they provide quite accurate estimation of the application performance in a fast way.
However, the estimation error has to be considered during design space exploration to evaluate if a solution can be accepted (e.g., by discarding solutions whose estimated time is too close to constraint).
Evaluate if the possible error can be significative analyzing a punctual estimation is not a trivial task.
In this paper we propose a methodology, based on statistical analysis, that provides a prediction interval on the estimation and a confidence level on the meeting of a time constraint.
This information can drive design space exploration reducing the number of solutions to be validated.
The results show how the produced intervals effectively capture the estimation error introduced by a linear model. |
| Title | Verifying Dynamic Power Management Schemes Using Statistical Model Checking |
| Author | Jayanand Asok Kumar, *Shobha Vasudevan (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 579 - 584 |
| Keyword | dynamic power management, statistical model checking, RTL, multicore |
| Abstract | Dynamic power management (DPM) schemes, such as power gating, are important runtime strategies for saving power in multicore architectures. Safety and efficiency are probabilistic properties which need to be verified in order to evaluate a DPM scheme. In this work, we employ statistical model checking to verify probabilistic properties on Register Transfer Level (RTL) descriptions of multicores. Statistical model checking performs a system-level verification of the DPM scheme by simulating several sample paths of the entire RTL design until the verification results lie within tolerable bounds of error. We illustrate our approach on the RTL of OpenSPARC T2, a publicly available industry-strength multicore processor. We verify the safety and efficiency properties of several power gating schemes by considering the power manageable blocks in the floating-point graphics unit. |
| Title | Formal Methods for Coverage Analysis of Architectural Power States in Power-Managed Designs |
| Author | *Aritra Hazra, Pallab Dasgupta (Indian Institute of Technology Kharagpur, India), Ansuman Banerjee (Indian Statistical Institute Kolkata, India), Kevin Harer (Synopsys Inc., U.S.A.) |
| Page | pp. 585 - 590 |
| Keyword | Formal Coverage Analysis, Formal Verification, Power Intent Verification, Assertions, Low-Power Designs |
| Abstract | The architectural power intent of a design defines the intended global power states of a power-managed integrated circuit. Verification of the implementation of power management logic involves the task of checking whether only the intended power states are reached. Typically, the number of global power states reachable by the global power management strategy is significantly lesser than the possible number of global power states. In this paper, we present a formal method for determining the set of reachable global power states in a power-managed design. Our approach demonstrates how this task can be further constrained as required by the verification engineer. We highlight the efficacy of the proposed methods over several test-cases. |