| Title | The Impact of Hot Carriers on Timing in Large Circuits |
| Author | Jianxin Fang, *Sachin Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 591 - 596 |
| Keyword | Hot Carrier Effects, Delay Degradation, Reliability Analysis, Static Timing Analysis |
| Abstract | This paper focuses on hot carrier (HC) effects in large scale digital circuits and proposes a scalable method for analyzing circuit-level delay degradations. At the transistor level, a multi-mode energy-driven model for nanometer technologies is employed. At the logic cell level, a methodology that captures the aging of a device as a sum of device age gains per signal transition is described, and the age gain is characterized using SPICE simulation. At the circuit level, the cell-level characterizations are used in conjunction with probabilistic methods to perform fast degradation analysis. The proposed analysis method is validated by Monte Carlo simulation on various benchmark circuits, and is proved to be accurate, efficient and scalable. |
| Title | A Learning-Based Autoregressive Model for Fast Transient Thermal Analysis of Chip-Multiprocessors |
| Author | *Da-Cheng Juan, Huapeng Zhou, Diana Marculescu, Xin Li (Carnegie Mellon University, U.S.A.) |
| Page | pp. 597 - 602 |
| Keyword | Thermal analysis, chip-multiprocessor, machine learning, autoregression, thermal optimization |
| Abstract | Thermal issues have become critical roadblocks for the development of advanced chip-multiprocessors. In this paper, we introduce a new angle to view transient thermal analysis – based on predicting thermal profile, instead of calculating it. We develop a systematic framework that can learn different thermal profiles of a CMP by an autoregressive model. Experimental results show that the proposed AR model can achieve 113X speed-up over existing thermal estimation methods, while introducing an error of only 0.8˚C on average. |
| Title | On-Chip Statistical Hot-Spot Estimation Using Mixed-Mesh Statistical Polynomial Expression Generating and Skew-Normal Based Moment Matching Techniques |
| Author | Pei-Yu Huang, Yu-Min Lee, *Chi-Wen Pan (National Chiao Tung University, Taiwan) |
| Page | pp. 603 - 608 |
| Keyword | Thermal Analysis, Thermal Yield, Process Variation, Leakage Powers, Thermal-Aware Design |
| Abstract | This work introduces the concept of thermal yield profile for the hot-spot identification with considering process variations and provides an efficient estimating technique for the thermal yield profile. After executing a mixed-mesh strategy for generating
statistical polynomial expression of the on-chip temperature distribution, the thermal yield profile is obtained by a skew-normal based moment matching technique. Comparing with the Monte Carlo method, experimental results demonstrate that our method can efficiently and accurately estimate the thermal yield profile.
With the same level of accuracy, our skew-normal based method achieves 215X speedup over the state of the art, APEX, for estimating the thermal yield profile. Moreover, results show that our mixed-mesh statistical polynomial expression generator achieves 130X speedup over the statistical collocation based method and still accurately estimates the thermal yield profile. |
| Title | Design Techniques for Functional-Unit Power Gating in the Ultra-Low-Voltage Region |
| Author | *Michael B. Henry, Leyla Nazhandali (Virginia Tech, U.S.A.) |
| Page | pp. 609 - 614 |
| Keyword | ultra low voltage operation, power gating, functional unit power gating, low power |
| Abstract | In this paper, we investigate many of the important aspects of highly aggressive functional unit power gating in the context of ultra-low-voltage operation. Using an optimization framework, we demonstrate that functional unit power gating results in an average of a 30-40% drop in total functional unit energy across a range of benchmarks. We also analyze Sense-Amplifier Pass Transistor Logic and show that compared to CMOS, SAPTL needs much smaller footers that are and consumes 100 times less boot-up energy. |