| Title | Post-Fabrication Reconfiguration for Power-Optimized Tuning of Optically Connected Multi-Core Systems |
| Author | Yan Zheng (Tsinghua University, China), *Peter Lisherness, Saeed Shamshiri, Amirali Ghofrani (University of California, Santa Barbara, U.S.A.), Shiyuan Yang (Tsinghua University, China), Kwang-Ting Tim Cheng (University of California, Santa Barbara, U.S.A.) |
| Page | pp. 615 - 620 |
| Keyword | Post-fabrication Reconfiguration, Optically connected Multi-core system, Reliability, Power Consumption, Design-for-Yield |
| Abstract | Integrating optical interconnects into the next-generation multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughput, latency, and power efficiency of electrical interconnects. Optical interconnects also allow the performance growth of inter-core connectivity to keep pace with the growth of the cores’ processing ability. However, variations in the fabrication process significantly impair an optical network’s communication quality. Existing post-fabrication tuning methods, which are based on adjusting the voltages and temperatures, have very limited tenability and require excessive power to fully compensate for the variation. In this paper, we study the sources and severity of process variation, and propose two methods to enhance the robustness of an on-chip optical network: 1) adding spare modulators and detectors for post-fabrication reconfiguration and low-power tuning, and 2) introducing a combined detector/modulator structure for a more robust network topology. Simulation results show that employing both methods can reduce the tuning power from hundreds of watts to 6W while maintaining a throughput of 99.7%. To maintain a throughput of 50%, the tuning power can be further reduced to only 12mW. |
| Title | GLOW: A Global Router for Low-Power Thermal-reliable Interconnect Synthesis using Photonic Wavelength Multiplexing |
| Author | Duo Ding, Bei Yu, *David Z. Pan (The University of Texas at Austin, U.S.A.) |
| Page | pp. 621 - 626 |
| Keyword | optical interconnect synthesis, low power, thermal reliability, physical design, nanophotonics WDM |
| Abstract | In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Division Multiplexing (WDM). With the recent advancements, it is foreseen that nanophotonics holds the promise to be employed for future on-chip data signalling due to its unique power efficiency, signal delay and huge multiplexing potential.
However, there are major challenges to address before feasible on-chip integration could be reached. We present GLOW, a hybrid global router to provide low power opto-electronic interconnect synthesis under the considerations of thermal reliability and various physical design constraints such as power(thermal), delay and signal quality. GLOW is simulated and evaluated on various testing cases derived from ISPD global routing contest benchmarks. Compared with a greedy heuristic approach, GLOW demonstrates 23%-50% of optical power reduction, revealing great potential of on-chip opto-electrical WDM interconnection. |
| Title | Charge Replacement in Hybrid Electrical Energy Storage Systems |
| Author | Qing Xie, Yanzhi Wang (University of Southern California, U.S.A.), Younghyun Kim, Donghwa Shin, *Naehyuck Chang (Seoul National University, Republic of Korea), Massoud Pedram (University of Southern California, U.S.A.) |
| Page | pp. 627 - 632 |
| Keyword | hybrid electrical energy storage, charge replacement, charge management |
| Abstract | Hybrid electrical
energy storage (HEES) systems are composed of multiple banks of
heterogeneous electrical energy storage (EES) elements with
distinctive properties. Charge replacement in a HEES system (i.e.,
dynamic assignment of load demands to EES banks) is one of the key
operations in the system. This paper formally describes the global
charge replacement (GCR) optimization problem and provides an
algorithm to find the near-optimal GCR control policy. The
optimization problem is formulated as a mixed-integer nonlinear
programming problem, where the objective function is the charge
replacement efficiency. The constraints account for the energy
conservation law, efficiency of the charger/converter, the rate
capacity effect, and self-discharge rates plus internal resistances
of the EES element arrays. The near-optimal solution to this problem
is obtained while considering the state of charges (SoCs) of the EES
element arrays, characteristics of the load devices, and estimates
of energy contributions by the EES element arrays. Experimental
results demonstrate significant improvements in the charge
replacement efficiency in an example HEES system comprised of banks
of battery and supercapacitor elements with a high-power pulsed
military radio transceiver as the load device. |
| Title | Prospects of Active Cooling with Integrated Super-Lattice based Thin-Film Thermoelectric Devices for Mitigating Hotspot Challenges in Microprocessors |
| Author | Borislav Alexandrov, Owen Sullivan, Satish Kumar, *Saibal Mukhopadhyay (Georgia Institute of Technology, U.S.A.) |
| Page | pp. 633 - 638 |
| Keyword | Thermoelectric Coolers, Hot Spot, Active Cooling |
| Abstract | Super-lattice thin-film thermoelectric coolers (TEC) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). The thermal compact models of the chip and package with integrated TECs are developed and used for steady-state and transient temperature analysis. The control principles for TEC assisted transient cooling are presented and their impact on reducing thermal violations in microprocessors and TEC energy dissipations are discussed. |