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The 17th Asia and South Pacific Design Automation Conference

Session 8B  Automated Debugging and Validation
Time: 14:00 - 15:40 Thursday, February 2, 2012
Location: Room 203
Chairs: Jiun-Lang Huang (National Taiwan University, Taiwan), Jai-Ming Lin (National Cheng Kung University, Taiwan)

8B-1 (Time: 14:00 - 14:25)
TitleA Formal Approach to Debug Polynomial Datapath Designs
Author*Bijan Alizadeh (University of Tehran, Iran)
Pagepp. 683 - 688
Keywordformal verification, debugging, polynomial datapath, mutation-based debugging
AbstractBy increasing the complexity of digital systems, debugging of such systems has become a major economical issue. In this paper, we introduce a mutation-based debugging technique that allows us to efficiently locate and then correct bugs in datapath dominated applications such as in Digital Signal Processing (DSP) for multimedia applications and embedded systems. In order to evaluate the effectiveness of our approaches, we have applied the proposed debugging technique to several industrial designs. The experimental results show that the proposed debugging technique enables us to localize and correct even multiple bugs in a reasonable run time and memory usage.

8B-2 (Time: 14:25 - 14:50)
TitleAutomated Debugging of Counterexamples in Formal Verification of Pipelined Microprocessors
Author*Miroslav N. Velev, Ping Gao (Aries Design Automation, U.S.A.)
Pagepp. 689 - 694
Keywordformal verification, pipelined processors, automated debugging, abstraction, SAT
AbstractWe propose a novel method for error diagnosis of pipelined microprocessors that allows us to exploit Positive Equality in Correspondence Checking. We also present static CNF variable ordering heuristics that dramatically reduce the solution space during the debugging. Experimental results indicate speedup of up to 2 orders of magnitude relative to previous approaches when applying the method to automated debugging in formal verification of complex pipelined DSPs.

8B-3 (Time: 14:50 - 15:15)
TitleOn Error Tolerance and Engineering Change with Partially Programmable Circuits
AuthorHratch Mangassarian (University of Toronto, Canada), Hiroaki Yoshida (University of Tokyo, Japan), Andreas Veneris (University of Toronto, Canada), Shigeru Yamashita (Ritsumeikan University, Japan), *Masahiro Fujita (University of Tokyo, Japan)
Pagepp. 695 - 700
KeywordYield enhancement, QBF, Engineering change, Stuck-at-fault
AbstractThe growing size, density and complexity of modern VLSI chips are contributing to an increase in hardware faults and design errors in the silicon, decreasing manufacturing yield and increasing the design cycle. The use of Partially Programmable Circuits (PPCs) has been recently proposed for yield enhancement with very small overhead. This new circuit structure is obtained from conventional logic by replacing some subcircuits with programmable LUTs. The present paper lays the theoretical groundwork for evaluating PPCs with Quantified Boolean Formula (QBF) satisfiability. First, QBF models are constructed to calculate the fault tolerance and design error tolerance of a PPC, namely the percentages of faults and design errors that can be masked using LUT reconfigurations. Next, zero-cost Engineering Change Order (ECO) in PPCs is investigated. QBF formulations are given for performing ECOs, and for quantifying the ECO coverage of a PPC architecture. Experimental results are presented evaluating PPCs from [1], demonstrating the applicability and accuracy of the proposed formulations.

8B-4 (Time: 15:15 - 15:40)
TitleOn Error Modeling of Electrical Bugs for Post-Silicon Timing Validation
AuthorMing Gao, *Peter Lisherness (University of California, Santa Barbara, U.S.A.), Jing-Jia Liou (National Tsing Hua University, Taiwan), Kwang-Ting (Tim) Cheng (University of California, Santa Barbara, U.S.A.)
Pagepp. 701 - 706
KeywordElectrical Bug, Post-silicon Validation, Error Model, Validation Metric
AbstractThere is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers' experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.