| Title | Hybrid Lithography Optimization with E-Beam and Immersion Processes for 16nm 1D Gridded Design |
| Author | Yuelin Du, Hongbo Zhang, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Kai-Yuan Chao (Intel Corporation, U.S.A.) |
| Page | pp. 707 - 712 |
| Keyword | Hybrid Lithography, E-Beam Lithography, 1-D Gridded Design, Cut Redistribution |
| Abstract | Since some of major IC industry participants are moving to the highly
regular 1D gridded designs to enable scaling to sub-20nm nodes, how
to manufacture the randomly distributed cuts with reasonable throughput and process variation becomes a big challenge. With the
help of hybrid lithography, people can apply different types of processes for one single layer manufacturing such that the advantages from different technologies can be combined together to further benefit manufacturing. In this paper, targeting cut printing difficulties and hybrid lithography with electron beam (E-Beam) and 193 nm immersion (193i) processes, we propose a novel
algorithm to optimally assign cuts to 193i or E-Beam processes with
proper modifications on cut distribution, in order to maximize the overall throughput. To validate our method, we construct our algorithm based on the forbidden patterns obtained from the optical simulation; then we formulate the redistribution problem into a well defined ILP
problem and finally call a reliable solver to solve the whole problem.
Experimental results show that the throughput is dramatically improved
by the cut redistribution. Besides that, for sparser layers, the EBL
process can be totaly saved, which largely reduces the fabrication cost. |
| Title | Design-Patterning Co-optimization of SRAM Robustness for Double Patterning Lithography |
| Author | Vivek Joshi (GLOBALFOUNDRIES, U.S.A.), *Dennis Sylvester (University of Michigan, U.S.A.), Kanak Agarwal (IBM Research, U.S.A.) |
| Page | pp. 713 - 718 |
| Keyword | Double Patterning, SRAM, yield |
| Abstract | This paper presents a comprehensive analysis and optimization framework that compares the layerwise impact of different Double Patterning Lithography (DPL) choices on SRAM robustness, density, and printability. It then performs a sizing optimization that accounts for increased variability due to DPL for each layer. Experimental results based on 45nm industrial models show that using the best DPL option for each layer, along with the sizing optimization presented, we can achieve single exposure robustness together with improved DPL printability at nearly no overhead (less than 0.2% increase in write energy). |
| Title | Efficient Pattern Relocation for EUV Blank Defect Mitigation |
| Author | Hongbo Zhang, Yuelin Du, *Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.), Rasit O. Topalaglu (GLOBALFOUNDRIES, U.S.A.) |
| Page | pp. 719 - 724 |
| Keyword | EUV, Defect Mitigation, Pattern Relocation |
| Abstract | Blank defect mitigation is a critical step for extreme ultraviolet (EUV) lithography. Targeting the defective blank, a layout relocation method, to shift and rotate the whole layout pattern to a proper position, has been proved to be an effective way to reduce defect impact. Yet, there is still no published work about how to find the best pattern location to minimize the impact from the buried defects with reasonable defect model and considerable process variation control. In this paper, we successfully present an algorithm
that can optimally solve this pattern relocation problem. Experimental results validate our method, and the relocation results with full scale layouts generated from Nangate Open Cell Library has shown great advantages with competitive runtimes compared to the existing commercial tool. |
| Title | Character Design and Stamp Algorithms for Character Projection Electron-Beam Lithography |
| Author | Peng Du, Wenbo Zhao, Shih-Hung Weng, *Chung-Kuan Cheng, Ronald Graham (University of California, San Diego, U.S.A.) |
| Page | pp. 725 - 730 |
| Keyword | Characters Projection, E-Beam Lithography, Character Design, Optimization Methods |
| Abstract | In this paper, we propose a series of methods, including character design, stencil compaction and layout matching for Character Projection (CP) Electron-Beam Lithography. We solve the problems with emphasis on inter-cell routing including wires and vias. For wire layout, we design a small set of regular characters after layout normalization. Then we partition the layout into several rows and adopt a greedy algorithm for layout matching in each row. For via layout, we utilize a minimum path covering algorithm to group vias into paths, which are contained in characters with bounded length. We devise an efficient method to compact all characters into a stencil with much less area than the total area of characters. Experimental results show that our algorithms achieve up to 83.42% and 67.29% of the maximum improved-throughput by CP against to Variable Shaped Beam (VSB) technology for wire and via layouts, respectively. Our characters can apply for general purpose layouts to save the high cost of generating different stencils for different layouts. |