| Title | BTI-Aware Design Using Variable Latency Units |
| Author | *Saket Gupta, Sachin Sapatnekar (University of Minnesota, U.S.A.) |
| Page | pp. 775 - 780 |
| Keyword | Variable Latency Design, Reliability, Throughput, Area |
| Abstract | Circuit degradation due to bias temperature instability (BTI) can lead to timing failures in digital circuits. We develop variable latency unit (VLU) based BTI-aware designs, with a novel scheme for multioutput hold logic implementation for VLUs. A key observation is the identification and exploitation of specific supersetting patterns in the two-dimensional space of frequency and aging of the circuit. The multioutput hold logic scheme is used in conjunction with an adaptive body bias framework to achieve high performance, allowing the design to be easily incorporated in traditional synthesis flows. As compared to conventional combinational BTI-resilience scheme, our design achieves an area reduction of 9.2%, with a significant throughput enhancement of 30.0%. |
| Title | Linear Decomposition of Index Generation Functions |
| Author | *Tsutomu Sasao (Kyushu Institute of Technology, Japan) |
| Page | pp. 781 - 788 |
| Keyword | linear transform, functional decomposition, code converter, random function, data compression |
| Abstract | This paper shows a heuristic method to reduce the number of variables to represent incompletely specified index generation functions using linear decompositions. To find good linear transformations, two measures are introduced: the imbalance measure and the ambiguity measure. Experimental results using m-out-of-n code to binary converters, randomly generated functions, IP address tables, and English word lists show the usefulness of the approach. |
| Title | Fixed-Point Accuracy Analysis of Datapaths with Mixed CORDIC and Polynomial Computations |
| Author | *Omid Sarbishei, Katarzyna Radecka (Dept. of Electrical and Computer Engineering, McGill University, Canada) |
| Page | pp. 789 - 794 |
| Keyword | Fixed-point format, polynomial datapaths, CORDIC units, precision analysis, range analysis |
| Abstract | Fixed-point accuracy analysis of imprecise datapaths in terms of Maximum-Mismatch (MM) [1], or Mean-Square-Error (MSE) [14], w.r.t. a reference model is a challenging task. Typically, arithmetic circuits are represented with polynomials; however, for a variety of functions, including trigonometric, hyperbolic, logarithm, exponential, square root and division, Coordinate Rotation Digital Computer (CORDIC) units can result in more efficient implementations with better accuracy. This paper presents a novel approach to robustly analyze the fixed-point accuracy of an imprecise datapath, which may consist of a combination of polynomials and CORDIC units. The approach builds a global polynomial for the error of the whole datapath by converting the CORDIC units and their errors into the lowest possible order Taylor series. The previous work for almost accurate analysis of MM [1] and MSE [14, 15] in large datapaths can only handle polynomial computations. |
| Title | Algorithm for Synthesizing Design Context-Aware Fast Carry-Skip Adders |
| Author | *Kiyoung Kim, Taewhan Kim (Seoul National University, Republic of Korea) |
| Page | pp. 795 - 800 |
| Keyword | timing, synthesis, optimization |
| Abstract | This work proposes a systematic synthesis algorithm of fast carry-skip adders which considers any arbitrary bit-level arrival times of the addends. We formulate the carry group partitioning problem for minimal timing into a dynamic programming problem and solved it effectively. The experimental results with various real arithmetic designs show that our synthesis algorithm is able to reduce the circuit latency by up to 16% and 10% compared to the best known existing algorithms. |