| Title | A 60-GHz 16QAM 11Gbps Direct-Conversion Transceiver in 65nm CMOS |
| Author | *Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chiavipas, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 467 - 468 |
| Keyword | CMOS, Direct-Conversion, Transceiver, 60GHz |
| Abstract | This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The 65nm CMOS transceiver realizes
the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in a package are 8Gbps in QPSK mode and 11Gbps in 16QAM mode within a BER of < 10-3. The transceiver consumes 186mW while transmitting, and 106mW while receiving. The PLL also consumes 66mW. |
| Title | A 120-mV Input, Fully Integrated Dual-Mode Charge Pump in 65-nm CMOS for Thermoelectric Energy Harvester |
| Author | *Po-Hung Chen, Koichi Ishida, Xin Zhang (The University of Tokyo, Japan), Yasuyuki Okuma, Yoshikatsu Ryu (Semiconductor Technology Academic Research Center, Japan), Makoto Takamiya, Takayasu Sakurai (The University of Tokyo, Japan) |
| Page | pp. 469 - 470 |
| Keyword | Charge pump, Startup, Low voltage, Dual-mode |
| Abstract | In this paper, a fully integrated low voltage charge pump for thermoelectric energy harvesters is presented. The proposed dual-mode architecture achieves both the low startup voltage in a startup mode and high conversion efficiency in a normal operation mode without off-chip inductors and capacitors. In the measurement, the proposed circuit successfully converts 120mV input to 770mV output with 38.8% conversion efficiency. |
| Title | CMA-2 : The Second Prototype of a Low Power Reconfigurable Accelerator |
| Author | *Mai Izawa, Nobuaki Ozaki, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano (Keio University, Japan) |
| Page | pp. 471 - 472 |
| Keyword | Reconfigurable System, Low Power Design, Real Chip Evaluation |
| Abstract | Cool Mega-Array (CMA) is a high energy-efficiency reconfigurable accelerator for battery-driven mobile devices. It consists of a large processing element (PE) array without memory elements for mapping the data-flow graph of the application being executed, a small simple programmable μ-controller for data management, and a data memory.
A prototype CMA chip (CMA-1) with 8×8 PE array was implemented with 65nm CMOS technology. CMA-1 has several limitations for testing as a real accelerator attached to the host CPU.
In order to relax the limitation of CMA-1, the second prototype chip (CMA-2) with 10×8 PE array was implemented with 40nm CMOS process.
Evaluation result with real chip shows that the maximum energy efficiency is 233.7MOPS/mW. |
| Title | Complexity-Effective Hilbert-Huang Transform (HHT) IP for Embedded Real-Time Applications |
| Author | Shyang-Chyun Chen, Chao-Chuan Chen, Wen-Chi Guo, *Tay-Jyi Lin, Ching-Wei Yeh (National Chung Cheng University, Taiwan) |
| Page | pp. 473 - 474 |
| Keyword | HHT, EMD, multirate signal processing |
| Abstract | This paper presents a complexity-effective HHT IP for embedded real-time applications. The proposed HHT improves the original empirical mode decomposition (EMD) to reduce the interferences between signal components with filtering, similar to that in the wavelet transform. The IMF and residue signals are compacted to reduce computation and storage. Multirate Hilbert spectral analysis (HSA) is performed to further reduce computations. A prototype of an embedded HHT analyzer has been built to demonstrate the effectiveness. |
| Title | Implementation of a Perpendicular MTJ-Based Read-Disturb-Tolerant 2T-2R Nonvolatile TCAM Based on a Reversed Current Reading Scheme |
| Author | *Shoun Matsunaga, Masanori Natsui, Shoji Ikeda (Center for Spintronics Integrated Systems, Tohoku University, Japan), Katsuya Miura (Hitachi Advanced Research Laboratory, Japan), Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu (Center for Spintronics Integrated Systems, Tohoku University, Japan) |
| Page | pp. 475 - 476 |
| Keyword | TCAM, nonvolatile, MTJ, power gating, standby power |
| Abstract | A perpendicular magnetic-tunnel-junction (MTJ)-based 2T-2R ternary content-addressable memory (TCAM) cell is proposed for a high-density nonvolatile word-parallel/bit-serial TCAM. The use of MOS/MTJ-hybrid logic makes it possible to implement a compact nonvolatile TCAM cell with 2.5 um2 of a cell size in a 0.14-um CMOS and a 100-nm perpendicular-MTJ technologies. By reversed-current reading through the perpendicular MTJ device, tolerability of read disturb is greatly enhanced. Moreover, fine-grained power gating based on bit-level equality-search scheme achieves ultra-low activity rate of 4.1 % in a fabricated 72-bit x 128-word nonvolatile TCAM, which results in ultra-low active power and standby power. |
| Title | Energy-Efficient RISC Design with On-Demand Circuit-Level Timing Speculation |
| Author | *Tay-Jyi Lin (National Chung Cheng University, Taiwan), Yu-Ting Kuo (Industrial Technology Research Institute, Taiwan), Yu-Jung Tsai, Ting-Yu Shyu (National Chung Cheng University, Taiwan), Yuan-Hua Chu (Industrial Technology Research Institute, Taiwan) |
| Page | pp. 477 - 478 |
| Keyword | circuit-level timing speculation, energy-efficient, low-power |
| Abstract | This paper presents an energy-efficient RISC design with a novel on-demand timing speculation mechanism, which is implemented with dual timing-relaxed datapaths. The proposed approach significantly reduces the design complexity and the overheads of existing double latching approaches, such as Razor. The design has been implemented and fabricated using the TSMC 65GP technology. Its supply voltage can be lowered to 0.6V for 300MHz operations with only 5.35% timing faults, all of which can be rescued with our proposed mechanism at some extra execution cycles. |
| Title | A 60mW Baseband SoC for CMMB Receiver |
| Author | *Chuan Wu, Jialin Cao, Dan Bao, Yun Chen, Xiaoyang Zeng (Fudan University, China) |
| Page | pp. 479 - 480 |
| Keyword | Baseband Processor, SoC, CMMB |
| Abstract | This paper describes baseband SoC implementation of China Mobile Multimedia Broadcasting (CMMB) receiver, which integrates analog to digital (ADC), physical layer (PHY) baseband processor and medium access control (MAC) processor in single silicon wafer. MAC functions are fully implemented by firmware on an embedded 32-bit RISC-based processor. In addition, several power management techniques are utilized to reduce the power consumption of baseband SoC. The baseband SoC was successfully fabricated in 0.13µm one-poly six-metal (1P6M) CMOS process. Both analog and digital circuits are integrated on 4.8×4.8 mm2 die consuming 60mW total power dissipation under 1.2V and 3.3V supplies. The experiment results reveal the proposed baseband SoC has excellent performance under the multipath channels. |