| Title | A Reference-Free On-Chip Timing Jitter Measurement Circuit Using Self-Referenced Clock and a Cascaded Time Difference Amplifier in 65nm CMOS |
| Author | *Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Daiki Hirabayashi, Takahiro J. Yamaguchi, Haruo Kobayashi (Gunma University, Japan) |
| Page | pp. 553 - 554 |
| Keyword | jitter, on-chip measurement, CMOS, time difference amplifier, BIST |
| Abstract | This paper demonstrates a reference-clock-free, high-resolution on-chip timing jitter measurement circuit. It combines a self-referenced clock and a cascaded time difference amplifier (TDA), which results in reference-clock-free, high-resolution timing jitter measurement without sacrificing operational speed. The test chip was designed and fabricated in 65 nm CMOS. Measured results of the proposed circuit show the possibility of detecting a timing jitter of 1.61-ps RMS in 820 MHz clock with less than 4% error. |
| Title | Simultaneous Data and Power Transmission using Nested Clover Coils |
| Author | *Yasuhiro Take, Hayun Chung, Noriyuki Miura, Tadahiro Kuroda (Keio University, Japan) |
| Page | pp. 555 - 556 |
| Keyword | power delivery, non-contact memory card, inductive-coupling, wireless |
| Abstract | This paper presents a simultaneous data and power transmission utilizing inductive-coupling interfaces for a non-contact memory card application. Nested clover coils are proposed to reduce interference from a power link. In order to maximize power transfer efficiency, the power transmitter tracks and predicts power consumption patterns of the memory card, and adjusts power transfer level. A test-chip prototype fabricated in a 65 nm CMOS process demonstrates 6 Gb/s data rate and 10% power transfer efficiency across a 0.1-2 kΩ load range. |
| Title | Complexity-Effective Auditory Compensation with a Controllable Filter for Digital Hearing Aids |
| Author | Ya-Ting Chang, *Kuo-Chiang Chang, Yu-Ting Kuo, Chih-Wei Liu (National Chiao Tung University, Taiwan) |
| Page | pp. 557 - 558 |
| Keyword | hearing aids, auditory compensation, low complexity |
| Abstract | Auditory compensation consumes significant power due to the computation-intensive operations in the filter bank. To reduce the complexity, a controllable filter was designed to replace the filter bank. Filter order was designed to match prescriptions within a specific error constraint with minimum computational cost. An interpolation scheme according to the variation of signal intensity was implemented to reduce the overhead of coefficients calculations. The proposed auditory compensation reduces 80% of multiplications and 30% of power consumption compared to the complexity-effective multi-rate filter bank architecture [4]. Moreover, the group delay was also reduced from 10 ms to 2.4 ms. |
| Title | A Progressive Mixing 20GHz ILFD with Wide Locking Range for Higher Division Ratios |
| Author | *Ahmed Musa, Kenichi Okada, Akira Matsuzawa (Tokyo Institute of Technology, Japan) |
| Page | pp. 559 - 560 |
| Keyword | ILFD, injection locking, frequency dividers, wide locking, divide by 4 |
| Abstract | This paper proposes Progressive Mixing Injection Locked Frequency Divider (PMILFD) technique that enhances the locking range for higher division ratios. As this technique uses lower and much stronger harmonics in the mixing process, it results in a stronger injection effect and a much wider locking range. Two 20GHz PMILFDs were designed based on this approach to divide by 4 and 8 using a 65nm CMOS process. The former achieves a 7.9GHz(31.4%) locking range and the later achieves a 3.4GHz(15.5%) while consuming 3.9mW. |
| Title | A 16-Gb/s Area-Efficient LD Driver with Interwoven Inductor in a 0.18-µm CMOS |
| Author | *Takeshi Kuboki (Kyoto University, Japan), Yusuke Ohtomo (NTT Microsystem Integration Laboratories, Japan), Akira Tsuchiya (Kyoto University, Japan), Keiji Kishine (University of Shiga Prefecture, Japan), Hidetoshi Onodera (Kyoto University, Japan) |
| Page | pp. 561 - 562 |
| Keyword | LD Driver, intewoven, inductor |
| Abstract | This paper presents the fastest laser-diode driver with interwoven peaking
inductor in 0.18-um CMOS.
Six and four inductors are interwoven into two sets of inductors for
area-effective implementation as well as performance enhancement.
The operation speed enhancement of the proposed circuit is achieved by
tuning mutual inductances of interwoven inductors.
The circuit area is 0.34-mm2 and the maximum operating speed is 16-Gb/s. |
| Title | A Single-Routing Layered LDPC Decoder for 10Gbase-T Ethernet in 130nm CMOS |
| Author | *Dan Bao, Xubin Chen, Yuebin Huang, Chuan Wu, Yun Chen, Xiao Yang Zeng (Fudan University, China) |
| Page | pp. 565 - 566 |
| Keyword | LDPC, Decoder |
| Abstract | A highly-parallel LDPC decoder architecture for 10Gbase-T applications is designed in this paper. Firstly, we reduce the routing complexity and corresponding power consumption by the proposed decoder architecture based on single routing networks. Secondly, the proposed architecture is designed with pipelined layered scheduling and multi-block parallel decoding, which improves operation speed and removes pipeline stalls in conventional highly-parallel layered scheduling. Thirdly, we trade off between hardware cost and throughput by a digit-serial data-path. Fourthly, an efficient early-termination circuit suitable for layered decoding is designed. The decoder is implemented in 130nm 1P8M CMOS process. The core area is 18.4mm2 with 14% reduction, and the decoding throughput is 9.48Gbps operating at 278MHz and 5 iterations. The tested power consumption is 774mW at 1.2V and 80MHz. |