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The 17th Asia and South Pacific Design Automation Conference

Session S1  Special Session 1: Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues
Time: 14:00 - 15:40 Tuesday, January 31, 2012
Location: Room 204A
Chair: Martin D.F. Wong (University of Illinois at Urbana-Champaign, U.S.A.)

S1-1
Title(Invited Paper) Robust and Resilient Designs from the Bottom-Up: Technology, CAD, Circuit, and System Issues
AuthorVijay J. Reddi, David Z. Pan (University of Texas at Austin, U.S.A.), Sani Nassif (IBM, U.S.A.), Keith A. Bowman (Intel, U.S.A.)
Pagepp. 7 - 16
Keywordresilient
AbstractThe semiconductor industry is facing a critical research challenge: design future high performance and energy efficient systems while satisfying historical standards for reliability and lower costs. The primary cause of this challenge is device and circuit parameter variability, which results from the manufacturing process and system operation. As technology scales, the adverse impact of these variations on system-level metrics increases. In this paper, we describe an interdisciplinary effort toward robust and resilient designs that mitigate the effects of device and circuit parameter variations in order to enhance system performance, energy efficiency, and reliability. Collaboration between the technology, CAD, circuit, and system levels of the compute hierarchy can foster the development of cost-effective and efficient solutions.

S1-2 (Time: 14:00 - 14:25)
Title(Invited Paper) Technology Challenges beyond 22nm
Author*Sani Nassif (IBM, U.S.A.)

S1-3 (Time: 14:25 - 14:50)
Title(Invited Paper) Physical CAD for Robust Designs
Author*David Z. Pan (University of Texas at Austin, U.S.A.)

S1-4 (Time: 14:50 - 15:15)
Title(Invited Paper) Resilient Circuit Design Trade-Offs for Improving Performance & Energy Efficiency
Author*Keith A. Bowman (Intel, U.S.A.)

S1-5 (Time: 15:15 - 15:40)
Title(Invited Paper) Coordinated System Design for Resiliency
Author*Vijay J. Reddi (University of Texas at Austin, U.S.A.)