| Title | (Invited Paper) Accelerated Processing and the Fusion System Architecture |
| Author | *Mike O'Connor (AMD Research, Texas, U.S.A.) |
| Page | p. 93 |
| Keyword | Fusion System Architecture |
| Abstract | Fusion System Architecture (FSA) is an open, extensible architecture that unifies CPUs and GPUs in a flexible computing fabric. New and existing programming languages and tools can build upon this framework to enable applications that seamlessly move between CPU and GPU cores, exploiting the best attributes of each. The architecture addresses low overhead data and computation transfer, as well as integrated manageability. |
| Title | (Invited Paper) Platform Characterization for Domain-Specific Computing |
| Author | *Alex Bui (Department of Radiological Sciences, University of California, Los Angeles, U.S.A.), Kwang-Ting (Tim) Cheng (Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A.), Jason Cong (Department of Computer Science, University of California, Los Angeles, U.S.A.), Luminita Vese (Department of Mathematics, University of California, Los Angeles, U.S.A.), Yi-Chu Wang (Department of Electrical and Computer Engineering, University of California, Santa Barbara, U.S.A.), Bo Yuan, Yi Zou (Department of Computer Science, University of California, Los Angeles, U.S.A.) |
| Page | pp. 94 - 99 |
| Keyword | Domain specific computing |
| Abstract | We believe that by adapting architectures to fit the requirements of a given application domain, we can significantly improve the efficiency of computation. To validate the idea for our application domain, we evaluate a wide spectrum of commodity computing platforms to quantify the potential benefits of heterogeneity and customization for the domain-specific applications. In particular, we choose medical imaging as the application domain for investigation, and study the application performance and energy efficiency across a diverse set of commodity hardware platforms, such as general-purpose multi-core CPUs, massive parallel many-core GPUs, low-power mobile CPUs and fine-grain customizable FPGAs. This study leads to a number of interesting observations that can be used to guide further development of domain-specific architectures. |
| Title | (Invited Paper) GreenDroid: An Architecture for the Dark Silicon Age |
| Author | Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng, Vikram Bhatt, Joe Auricchio, Steven Swanson, *Michael Bedford Taylor (University of California, San Diego, U.S.A.) |
| Page | pp. 100 - 105 |
| Keyword | greendroid, utilization wall, c-core, dark silicon |
| Abstract | Our research attacks the Dark Silicon problem directly through a set of energy-saving accelerators, called Conservation Cores, or c-cores. C-cores are a post-multicore approach that constructively uses dark silicon to reduce the energy consumption of an application by 10x or more. To examine the utility of c-cores, we are developing GreenDroid, a multicore chip that targets the Android mobile software stack. Our mobile application processor prototype targets a 32-nm process and is comprised of hundreds of automatically generated, specialized, patchable c-cores. These cores target specific Android hotspots, including the kernel. Our preliminary results suggest that we can attain large improvements in energy efficiency using a modest amount of silicon. |
| Title | (Invited Paper) Accelerator-Rich Architectures: Implications, Opportunities and Challenges |
| Author | *Ravi Iyer (Intel, U.S.A.) |
| Page | pp. 106 - 107 |
| Keyword | accelerators |
| Abstract | Providing high performance at ultra-low power for a domain of applications is possible by designing and integrating accelerators. Accelerators may be fixed-function, programmable or re-configurable in nature. Integration of many such accelerators in a system-on-chip (SoC) or chip-multiprocessor (CMP) introduces several major implications on architecture, power/performance and programmability. In this paper, we will provide an overview of the key challenges and outline research opportunities and challenges for accelerator-rich architectures and devices. We will also describe example solutions in some of these areas as a potential direction for further exploration. |
| Title | (Invited Paper) A Reconfigurable Platform for the Design and Verification of Domain-Specific Accelerators |
| Author | Sungho Park, Yong Cheol, Peter Cho, Kevin M. Irick, *Vijaykrishnan Narayanan (The Pennsylvania State University, U.S.A.) |
| Page | pp. 108 - 113 |
| Keyword | accelerators |
| Abstract | In this paper we present Vortex: a reconfigurable Network-on- Chip platform suitable for implementing domain-specific hardware accelerators in a design efficient manner. Our Vortex platform provides a flexible means to compose domain-specific accelerators for streaming applications such as performance critical machine vision systems. By substituting a traditional shared-bus architecture with low latency packet-switched routers and high utility network adaptors, maximum performance is exploited with minimal regard to communication infrastructure design and validation. To highlight the utility of the Vortex platform we present a case study in which a video analytics pipeline is mapped onto a multi-FPGA system. The system meets real-time throughput requirements on 3 Megapixel 48-bit image sequences with minimal resource overhead attributed to the Vortex communication infrastructure. |