| Title | (Invited Paper) Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs |
| Author | Sascha Roloff, Frank Hannig, Jürgen Teich (Department of Computer Science University of Erlangen-Nuremberg, Germany) |
| Page | pp. 187 - 192 |
| Keyword | MPSoC |
| Abstract | The design and the programming of heterogeneous future MPSoCs including thousands of processor cores is a hard challenge. Means are necessary to program and simulate the dynamic behavior of such systems in order to dimension the hardware design and to verify the software functionality as well as performance goals. Cycle-accurate simulation of multiple parallel applications simultaneously running on different cores of the architecture would be much too slow and is not the desired level of detail. In this paper, we therefore present a novel high-level simulation approach which tackles the complexity and the heterogeneity of such systems and enables the investigation of a new computing paradigm called invasive computing. Here, the workload and its distribution are not known at compile-time but are highly dynamic and have to be adapted to the status (load, temperature, etc.) of the underlying architecture at run-time. We propose an approach for the modeling of tiled MPSoC architectures and the simulation of resource-aware programming concepts on these. This approach delivers important timing information about the parallel execution and also is taking into account the computational properties of possibly different types of cores. |
| Title | (Invited Paper) Invasive Manycore Architectures |
| Author | Jörg Henkel (Karlsruhe Institute of Technology, Germany), Andreas Herkersdorf (Technical University of Munich, Germany), Lars Bauer (Karlsruhe Institute of Technology, Germany), Thomas Wild (Technical University of Munich, Germany), Michael Hubner (Karlsruhe Institute of Technology, Germany), Ravi Kumar Pujari (Technical University of Munich, Germany), Artjom Grudnitsky, Jan Heisswolf (Karlsruhe Institute of Technology, Germany), Aurang Zaib (Technical University of Munich, Germany), Benjamin Vogel (Karlsruhe Institute of Technology, Germany), Vahid Lari (University of Erlangen-Nuremberg, Germany), Sebastian Kobbe (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 193 - 200 |
| Keyword | invasive computing, manycore architectures |
| Abstract | This paper introduces a scalable hardware and software platform applicable for demonstrating the benefits of the invasive computing paradigm. The hardware architecture consists of a heterogeneous, tile-based manycore structure while the software architecture comprises a multi-agent management layer underpinned by distributed runtime and OS services. The necessity for invasive-specific hardware assist functions is analytically shown and their integration into the overall manycore environment is described. |
| Title | (Invited Paper) Hardware Prototyping of Novel Invasive Multicore Architectures |
| Author | Jürgen Becker, Stephanie Friederich, Jan Heisswolf, Ralf Koenig (Karlsruhe Institute of Technology, Germany), David May (Technische Universität München, Germany) |
| Page | pp. 201 - 206 |
| Keyword | invasive computing |
| Abstract | The sustained advance in technology will enable integrating hundreds of processing cores on a single die in near future. However, it already can be foreseen that the management of the resources of such large systems will not scale in the same way as the hardware using todays entirely software based and centralized management approaches. The invasive paradigm addresses this problem and proposes concepts to enable resource awareness and scalability – especially focusing the resource management perspective – in future multicore systems. These concepts are based on distributed and software-hardware partitioned resource management strategies. High level management decision that are made by software thereby trigger lower level management strategies that are autonomously carried out in hardware. Sufficiently accurate modeling of the overall invasive system is required to study and optimize such a decentralized, software-hardware partitioned control loop where decisions significantly depend on runtime dynamic effects. Software based simulation cannot deliver the required speed or accuracy making FPGA based prototyping of invasive systems necessary. This paper describes our prototyping concepts and discusses possible implementation alternatives for invasive multicore architectures. |
| Title | (Invited Paper) Invasive Computing for Robotic Vision |
| Author | Johny Paul, Walter Stechele (Technical University of Munich, Germany), M. Kröhnert, T. Asfour, R. Dillmann (Karlsruhe Institute of Technology, Germany) |
| Page | pp. 207 - 212 |
| Keyword | invasive computing |
| Abstract | Most robotic vision algorithms are computationally intensive and operate on millions of pixels of real-time video sequences. But they offer a high degree of parallelism that can be exploited through parallel computing techniques like Invasive Computing. But the conventional way of multi-processing alone (with static resource allocation) is not sufficient enough to handle a scenario like robotic maneuver, where processing elements have to be shared between various applications and the computing requirements of such applications may not be known entirely at compile-time. Such static mapping schemes leads to inefficient utilization of resources. At the same time it is difficult to dynamically control and distribute resources among different applications running on a single chip, achieving high resource utilization under high-performance constraints. Invasive Computing obtains more importance under such circumstances, where it offers resource awareness to the application programs so that they can adapt themselves to the changing conditions, at run-time. In this paper we demonstrate the resource aware and self-organizing behavior of invasive applications using three widely used applications from the area of robotic vision - Optical Flow, Object Recognition and Disparity Map Computation. The applications can dynamically acquire and release hardware resources, considering the level of parallelism available in the algorithm and time-varying load. |