| Title | (Invited Paper) Abstract System-Level Models for Early Performance and Power Exploration |
| Author | *Andreas Gerstlauer, Suhas Chakravarty, Manan Kathuria, Parisa Razaghi (The University of Texas at Austin, U.S.A.) |
| Page | pp. 213 - 218 |
| Keyword | System-level models, Host-compiled modeling, Design Space Exploration |
| Abstract | With increasing complexity of today’s embedded systems, research has focused on developing fast, yet accurate high-level and executable models of complete platforms. These models address the need for hardware/software co-simulation of the entire system at early stages of the design. Traditional models tend to be either slow or inaccurate. In this paper, we present ingredients for a class of abstract, high-level platform models that enable fast yet accurate performance and power simulation of application execution on heterogeneous multi-core/-processor architectures. Models are based on host-compiled simulation of the application code, which is instrumented with timing and power information. Back-annotated source code is further augmented with abstract OS and processor models that are integrated into standard co-simulation backplanes. The efficiency of the modeling platform has been evaluated by applying an industrial-strength benchmark, demonstrating the feasibility and benefits of such models for rapid, early exploration of the power, performance and cost design space. Results show that an accurate Pareto set of solutions can be obtained in a fraction of the time needed with traditional simulation and modeling approaches. |
| Title | (Invited Paper) Virtual Prototyping of Cyber-Physical Systems |
| Author | *Wolfgang Mueller, Markus Becker, Ahmed Elfeky (University of Paderborn/C-LAB, Germany), Anthony DiPasquale (Northwestern University, U.S.A.) |
| Page | pp. 219 - 226 |
| Keyword | cyber-physical systems, SystemC, QEMU |
| Abstract | The modeling and analysis of Cyber-Physical Systems (CPS) is one of the key challenges in complex system design as heterogeneous components are combined and their close interaction with the physical environment has to be considered. This article presents a methodology and an open toolset for the virtual prototyping of CPS. The focus of the methodology is the virtual prototyping of the embedded software combined with the prototyping of the physical environment in order to capture the complete closed control loop of the software over the hardware via sensors/actors with the physical objects. The methodology is based on the application of integrated open source tools and standard languages, i.e., C/C++, SystemC, and the Open Dynamics Engine, which are combined to a powerful simulation framework. Key activities of the methodology are outlined by the example of an electric two-wheel vehicle. |
| Title | (Invited Paper) Parallel Discrete Event Simulation of Transaction Level Models |
| Author | *Rainer Doemer, Weiwei Chen, Xu Han (Center for Embedded Computer Systems, University of California, Irvine, U.S.A.) |
| Page | pp. 227 - 231 |
| Keyword | MPSoC, PDES, SystemC, SpecC |
| Abstract | Describing Multi-Processor Systems-on-Chip (MPSoC) at the abstract Electronic System Level (ESL) is one task, validating them efficiently is another. Here, fast and accurate system-level simulation is critical. Recently, Parallel Discrete Event Simulation (PDES) has gained significant attraction again as it promises to utilize the existing parallelism in today’s multi-core CPU hosts. This paper discusses the parallel simulation of Transaction-Level Models (TLMs) described in System-Level Description Languages (SLDLs), such as SystemC and SpecC. We review how PDES exploits the explicit parallelism in the ESL design models and uses the parallel processing units available on multi-core host PCs to significantly reduce the simulation time. We show experimental results for two highly parallel benchmarks as well as for two actual embedded applications. |
| Title | (Invited Paper) Post-Silicon Patching for Verification/Debugging with High-Level Models and Programmable Logic |
| Author | *Masahiro Fujita, Hiroaki Yoshida (VLSI Design and Education Center (VDEC), University of Tokyo/CREST, Japan Science and Technology Agency, Japan) |
| Page | pp. 232 - 237 |
| Keyword | high-level models |
| Abstract | Due to continuous increase of design complexity in SoC development, the time required for post-silicon verification and debugging keeps increasing especially for electrical errors and very corner case bugs (which happen in extreme rare but actual situations), and it is now understood that some sort of programmability in silicon is essential to reduce the time for post-silicon verification and debugging. In this paper, we discuss partial use of in-field programmability in control parts of circuits for post-silicon debugging processes for electrical errors and corner case logical bugs. Our method deals with RTL designs in FSMD (Finite State Machine with Datapath) by adding partially in-field programmability, called "patch logic", in their control parts. If designs are given in high level like Cbased designs, by using our high level synthesis techniques, they are first synthesized to include such in-field programmability in the control parts of the synthesized RTL automatically. With patch logic we can dynamically change the behaviors of circuits in such a way that state transition sequences as well as values of internal values are traced based on user requests. Our patch logic can also check if there is an electrical errors or not periodically. Assuming that electrical errors occur very infrequently, an error can be detected by comparing the equivalence on the results of duplicated computations. Through experiments we discuss the area, timing, and power overhead due to the patch logic and also show results on electrical error detection with duplicated computations. |