| Title | (Invited Paper) Bug Localization Techniques for Effective Post-Silicon Validation |
| Author | *Subhasish Mitra, David Lin (Stanford University, U.S.A.), Nagib Hakim, Don Gardner (Intel Corporation, U.S.A.) |
| Page | p. 291 |
| Keyword | bug localization |
| Abstract | Post-silicon validation is used to detect and fix bugs in integrated circuits and systems after manufacture. Due to sheer design complexity, it is nearly impossible to detect and fix all bugs before manufacture. Existing post-silicon validation methods barely cope with today’s complexity. New techniques are essential to minimize the effects of bugs and design flaws going forward. This talk will focus on two recent techniques, QED and IFRA, that can overcome significant challenges associated with a very crucial step in post-silicon validation: bug localization in a system setup. We demonstrate the effectiveness of these techniques using results from quad-core Intel Core i7 hardware platforms and Intel Nehalem processors, and using actual examples of "difficult" bugs that occurred in complex SoCs. |
| Title | (Invited Paper) Improving Validation Coverage Metrics to Account for Limited Observability |
| Author | *Peter Lisherness, Kwang-Ting (Tim) Cheng (Electrical and Computer Engineering Department, UCSB, U.S.A.) |
| Page | pp. 292 - 297 |
| Keyword | observability, coverage metrics |
| Abstract | In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the behavior as erroneous. Most functional and code coverage metrics evaluate only the activation component of the testbench and ignore propagation and detection. In this paper, we summarize our recent work in developing improved metrics that account for propagation and/or detection of design errors. These works include tools for observability-enhanced code coverage and mutation analysis of high-level designs as well as an analytical method, Coverage Discounting, which adds checker sensitivity to arbitrary functional coverage metrics. |
| Title | (Invited Paper) Automated Data Analysis Techniques for a Modern Silicon Debug Environment |
| Author | *Yu-Shen Yang (Vennsa Technologies, Canada), Andreas Veneris (Department of ECE and Department of CS, University of Toronto, Canada), Nicola Nicolici (Department of ECE, McMaster University, Canada), Masahiro Fujita (VLSI Design and Education Center, University of Tokyo, Japan) |
| Page | pp. 298 - 303 |
| Keyword | silicon debug |
| Abstract | With the growing size of modern designs and more strict time-to-market constraints, design errors unavoidably escape pre-silicon verification and reside in silicon prototypes. As a result, silicon debug has become a necessary step in the digital integrated circuit design flow. Although embedded hardware blocks, such as scan chains and trace buffers, provide a means to acquire data of internal signals in real time for debugging, there is a relative shortage in methodologies to efficiently analyze this vast data to identify root-causes. This paper presents an automated software solution that attempts to fill-in the gap. The presented techniques automate the configuration process for trace-buffer based hardware in order to acquire helpful information for debugging the failure, and detect suspects of the failure in both the spatial and temporal domain. |
| Title | (Invited Paper) Optimizing Test-Generation to the Execution Platform |
| Author | Amir Nahir, *Avi Ziv (IBM Research, Haifa, Israel), Subrat Panda (IBM Systems and Technology Group, Bangalore, India) |
| Page | pp. 304 - 309 |
| Keyword | test generation |
| Abstract | The role of stimuli generators is to reach all the dark corners of the design and expose the bugs hiding there. As such, stimuli generation is one of the cornerstones of dynamic verification. The quality of tools used for stimuli generation affect the outcome of the verification process. This paper discusses how differences between execution platforms, ranging from software simulators, through accelerators and emulators, to silicon affect the requirements of stimuli generators and how stimuli generators targeting different execution platforms address these differences. We demonstrate how the unique added value of the platforms are combined to guarantee the high quality of the silicon using examples of several IBM pre- and post-silicon stimuli generators with results from the verification of the IBM POWER7 processor chip. |