| Title | (Invited Paper) When to Forget: A System-level Perspective on STT-RAMs |
| Author | *Karthik Swaminathan, Raghav Pisolkar, Cong Xu, Vijaykrishnan Narayanan (Dept. of Computer Science and Engineering, The Pennsylvania State University, U.S.A.) |
| Page | pp. 311 - 316 |
| Keyword | STT-RAM |
| Abstract | The benefits of using STT-RAMs as an alternative to SRAMs are being examined in great detail. However their comparatively higher write latencies and energies continue to be roadblocks for migrating to MRAM based technology in memory hierarchies. In this paper, we present a novel method by which we demonstrate significant energy reduction in writing to the STT-RAM cell by relaxing its non-volatility property. We exploit this characteristic for optimizing system-level properties such as garbage collection. By categorizing the objects based on their lifetimes it is possible to tune the data retention time of the STTRAM to minimize the write energy. Our scheme yielded 37% reduction in dynamic energy, 88% reduction in leakage and 85% improvement in the Energy-Delay Product over a corresponding SRAM based memory structure. |
| Title | (Invited Paper) Write-Activity-Aware Page Table Management for PCM-based Embedded Systems |
| Author | Tianzheng Wang, Duo Liu, *Zili Shao (The Hong Kong Polytechnic University, Hong Kong), Chengmo Yang (University of Delaware, U.S.A.) |
| Page | pp. 317 - 322 |
| Keyword | PCM, Memory Management, Android, Operating Systems, Page Table |
| Abstract | Due to its low power consumption and high density, phase change memory (PCM) becomes a promising main memory alternative to DRAM in embedded systems. PCM, however, has the endurance problem in which the number of rewrites to each cell is quite limited compared with DRAM. Therefore, it is fundamental to eliminate unnecessary writes in PCM-based embedded systems. This paper presents a simple yet effective scheme to solve this problem, through redesigning existing software to exploit the write-activity-aware feature provided by the underlying hardware. In particular, we target at the page table management, a key kernel component residing in the memory management part of the Linux kernel. We present for the first time a write-activity-aware page table management scheme, WAPTM, accomplished through two simple modifications to the page table initialization and the page frame allocation process. The scheme has been implemented in Google Android 2.3 based on ARM architecture and evaluated with real applications on the Android emulator. The experimental results show that the proposed scheme can significantly reduce write activities to page tables in the new kernel compared with the original Android. We hope this work can serve as a first step towards the design of write-activity-aware operating systems via simple and feasible modifications. |
| Title | (Invited Paper) Probabilistic Design in Spintronic Memory and Logic Circuit |
| Author | *Yiran Chen, Yaojun Zhang, Peiyuan Wang (Dept. of ECE, University of Pittsburgh, U.S.A.) |
| Page | pp. 323 - 328 |
| Keyword | spintronic |
| Abstract | Spin-transfer torque random access memory (STTRAM) is a promising candidate for next-generation non-volatile memory technologies. It combines many attractive attributes such as nanosecond access time, high integration density, non-volatility, and good CMOS process compatibility. However, process variation continues to be a critical issue in the designs of STT-RAM and the derived spintronic logic. Besides the process-variationinduced persistent operation error, the non-persistent error that is incurred by the intrinsic thermal fluctuations of Magnetic Tunneling Junction (MTJ) devices significantly influences the spintronic circuit reliability. In this paper, we analyzed these two types of STT-RAM operation errors at both single cell and array levels. On the top of that, we quantitatively investigate the impacts of these errors on a nonvolatile spintronic flip-flop design. Some possible design techniques to reduce the operation error rate are also discussed. Our experimental results show that a statistical design technique must be adopted in spintronic memory and logic designs to achieve the desired operation reliability. We refer this technique as “probabilistic design”. |
| Title | (Invited Paper) Endurance-Aware Circuit Designs of Nonvolatile Logic and Nonvolatile SRAM Using Resistive Memory (Memristor) Device |
| Author | *Meng-Fan Chang, Ching-Hao Chuang, Min-Ping Chen, Lai-Fu Chen (Department of Electrical Engineering, National Tsing Hua University, Taiwan), Hiroyuki Yamauchi (Department of Information Electronics, Fukuoka Institute of Technology, Japan), Pi-Feng Chiu, Shyh-Shyuan Sheu (Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute (ITRI), Japan) |
| Page | pp. 329 - 334 |
| Keyword | memristor |
| Abstract | The use of low voltage circuits and power-off mode help to reduce the power consumption of chips. Non-volatile logic (nvLogic) and nonvolatile SRAM (nvSRAM) enable a chip to preserve its key local states and data, while providing faster power-on/off speeds than those available with conventional two-macro schemes. Resistive memory (memristor) devices feature fast write speed and low write power. Applying memristors to nvLogic and nvSRAMs not only enables chips to achieve low power consumption for store operations, but also achieve fast power-on/off processes and reliable operation even in the event of sudden power failure. However, current memristor devices suffer from limited endurance, which influences the design of the circuit structure for memristor-based nvLogic and nvSRAM. Moreover, previous nvLogic/nvSRAM circuits cannot achieve low voltage operation. This paper explores various circuit structures for nvLogic and nvSRAM, taking into account memristor endurance, especially for low-voltage applications. |