| Title | (Invited Paper) Nano-Electro-Mechanical (NEM) Relays and their Application to FPGA Routing |
| Author | Chen Chen, Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Daesung Lee, Roger T. Howe, H.S. Philip Wong (Department of Electrical Engineering, Stanford University, U.S.A.), *Subhasish Mitra (Department of Electrical Engineering, Stanford University and Department of Computer Science, Stanford University, U.S.A.) |
| Page | p. 639 |
| Keyword | NEM, FPGA routing |
| Abstract | Nano-Electro-Mechanical (NEM) relays are nano-scale switches that can be mechanically actuated by an electrical signal. Unlike conventional CMOS transistors, NEM relays exhibit zero off-state leakage and very sharp on-off transitions. As a result, NEM relays can be potentially used to design highly energy-efficient digital systems. NEM relays are also excellent candidates for programmable routing switches in Field Programmable Gate Arrays (FPGAs) due to their potentially low on-state resistances despite their long mechanical delays. Low-temperature fabrication of NEM relays creates opportunities for their integration on top of silicon CMOS circuits. Hysteresis properties of NEM relays can enable their use as FPGA programmable routing switches without requiring additional routing SRAM cells. In this talk, we will present an overview of NEM relays and their use in digital system design, and discuss design considerations for hybrid CMOS-NEM FPGAs. |
| Title | (Invited Paper) Capturing the Phantom of the Power Grid – On the Runtime Adaptive Techniques for Noise Reduction |
| Author | Tao Wang (ECE Dept., Missouri University of Science and Technology, U.S.A.), Pei-Wen Luo, Yu-Shih Su, Liang-Chia Cheng, Ding-Ming Kwai (Industrial Technology Research Institute, Hsin-Chu, Taiwan), *Yiyu Shi (ECE Dept., Missouri University of Science and Technology, U.S.A.) |
| Page | pp. 640 - 645 |
| Keyword | Power Grid |
| Abstract | Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios. Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical design methodologies have been adapted, which may bring significant design overhead. In view of this, various runtime techniques have been proposed in literature to suppress power grid noise adaptively. This paper first presents various challenges in power grid designs from an industrial perspective, explains the difficulties in handling them at deign time, and then reviews various runtime techniques to adaptively suppress power supply noise, including sensor-based power gating, re-routable decaps, proactive clock frequency actuator, and PLL based clocking. |
| Title | (Invited Paper) Post Silicon Skew Tuning: Survey and Analysis |
| Author | Mac Y.C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, *Shih-Chieh Chang (NTHU, Taiwan) |
| Page | pp. 646 - 651 |
| Keyword | skew tuning |
| Abstract | Clock skew minimization is an important design consideration. However, with the advance of the technology and the smaller device scaling, Process, Voltage, and Temperature (PVT) variations make the clock skew minimization face great challenges. To mitigate the impact of PVT variations, many previous works proposed the Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture, there are two main components: Adjustable Delay Buffer (ADB) and Phase Detector (PD). In this paper, we make a survey about existing techniques to the PST architecture and introduce several important design concerns such as the ADB selection, system controlling, and design testing to the PST architecture. |
| Title | (Invited Paper) Compilation and Architecture Support for Customized Vector Instruction Extension |
| Author | *Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza (University of California, Los Angeles, U.S.A.) |
| Page | pp. 652 - 657 |
| Keyword | custom vector instruction |
| Abstract | Vectorization has been commonly employed in modern processors. In this work we identify the opportunities to explore customized vector instructions and build an automatic compilation flow to efficiently identify those instructions. A composable vector unit (CVU) is proposed to support a large number of customized vector instructions with small area overhead. The results show that our approach achieves an average 1.41X speedup over the state-of-art vector ISA. We also observe a large area gain (around 11.6X) over the dedicated ASIC-based design. |