| Title | (Invited Paper) Yield Enhancement for 3D-Stacked ICs: Recent Advances and Challenges |
| Author | *Qiang Xu, Li Jiang (The Chinese University of Hong Kong, Hong Kong), Huiyun Li (Shenzhen Institutes of Advanced Technology, China), Bill Eklow (Cisco Systems, U.S.A.) |
| Page | pp. 731 - 737 |
| Keyword | 3D-stacked ICs, Manufacturing yield, Defect tolerance, TSV |
| Abstract | Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the "known good die" problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future. |
| Title | (Invited Paper) On Test and Repair of 3D Random Access Memory |
| Author | Cheng-Wen Wu (National Tsing Hua University, Taiwan), *Shyue-Kun Lu (National Taiwan University of Science and Technology, Taiwan), Jin-Fu Li (National Central University, Taiwan) |
| Page | pp. 744 - 749 |
| Keyword | 3D Random Access Memory, Built-In Self-Repair, Yield-Enhancement, Built-In Self-Test |
| Abstract | The three-dimensional (3D) random access memory (RAM) using through-silicon via (TSV) has been considered as a promising approach to overcome the memory wall. However, cost and yield are two key issues for volume production of 3D RAMs, and yield enhancement increasingly requires test techniques. In this paper, we first introduce issues and existing techniques for the testing and yield enhancement of 3D RAMs. Then, a built-in self-repair (BISR) technique for 3D RAM using global redundancy is presented. According to the redundancy analysis results of each die with the BISR circuit, the die-to-die (d2d) and wafer-to-wafer (w2w) stacking problems are transferred to the bipartite maximal matching problem. Then, heuristic algorithms are also proposed to optimize the stacking yield. |
| Title | (Invited Paper) Design for Manufacturability and Reliability for TSV-based 3D-ICs |
| Author | *David Z. Pan (University of Texas at Austin, U.S.A.), Sung Kyu Lim, Krit Athikulwongse, Moongon Jung (Georgia Institute of Technology, U.S.A.), Joydeep Mitra, Jiwoo Pak (University of Texas at Austin, U.S.A.), Mohit Pathak (Georgia Institute of Technology, U.S.A.), Jae-seok Yang (University of Texas at Austin, U.S.A.) |
| Page | pp. 750 - 755 |
| Keyword | reliability, manufacturability, through-silicon-vias, 3D-IC |
| Abstract | The 3D IC integration using through-silicon-vias (TSV) has
gained tremendous momentum recently for industry adoption. However,
as TSV involves disruptive manufacturing technologies, new modeling
and design techniques need to be developed for 3D IC manufacturability
and reliability. In particular, TSVs in 3D IC may cause significant
thermal mechanical stress, which not only results in systematic mobility/
performance variations, but also leads to mechanical reliability
concerns such as interfacial cracking. Meanwhile, the huge dimensional
gaps between TSV, on-chip wires, and bonding/packaging all lead to
new electromigration concerns. Thus full-chip/package modeling and
physical design tools need to be developed to achieve more reliable
3D IC integration. In this paper, we will discuss some key design for
manufacturability and reliability challenges and possible solutions for
TSV-based 3D IC integration, as well as future research directions. |