Tutorials

The following tutorials will be held on January 30, 2012:

Tutorial 1: Design for Manufacturability and Reliability in Nanoscale CMOS and 3D-IC
Location: Bayside Room 204A

Organizer: David Z. Pan, University of Texas at Austin

Speakers:
  • David Z. Pan (Univ. of Texas at Austin, USA)
  • Sani Nassif (IBM Austin Research Lab, USA)
  • Sachin Sapatnekar (Univ. of Minnesota, USA)
  • Sung Kyu Lim (Georgia Institute of Technology, USA)
Description:

As CMOS feature size scales to 22nm, the IC manufacturability and reliability issues become key bottlenecks in design closure, manufacturing yield, and product life cycle. Meanwhile, the emerging 3D-IC integration with through-silicon vias (TSV) has its own unique challenges in the overall 3D-IC/package manufacturability and reliability. This tutorial will provide a broad yet in-depth overview of the cutting edge issues in design for manufacturability (DFM) and design for reliability (DFR) in nanoscale CMOS and 3D-IC. The topics to be covered include challenges, recent results and potential solutions for: (1) DFM with emerging nanopatterning such as double/multiple patterning and EUV/E-beam lithography, (2) dealing with variations in very deep-submicron circuits, (3) reliability modeling and optimization for extremely scaled CMOS such as NBTI/PBTI, hot carrier injection, and so on, and (4) 3D-IC reliability such as TSV-induced thermal mechanical stress, electromigration and cracking.

Outline:
  • Section 1: Design for Manufacturability with Emerging Nanolithography
  • Section 2: Modeling, simulation, and amelioration of the impact of manufacturing variability on circuits
  • Section 3: Reliability of Extremely Scaled CMOS
  • Section 4: 3D IC and TSV reliability: what are the burning issues and their potential solutions?

Tutorial 2: Wireless Body Sensor Network (WBSN) Design
Location: Bayside Terrace

Organizer: David Atienza, Embedded Systems Laboratory at EPFL, Switzerland

Speakers:
  • David Atienza (Director of Embedded Systems Laboratory at EPFL, Switzerland)
  • Nadia Khaled (Senior Scientist at EPFL-Nestlé Research Center Lausanne, Switzerland)
  • Edith Beigné (Head of the Low Power Design Team at CEA-LETI, France)
  • Cyril Condemine (Head of the Microsystems IC design Laboratory at CEA-LETI, France)
  • Elisabetta Farella (Senior Research Fellow at Department of Electronics, Computer Science and Systems (DEIS) University of Bologna, Italy)
Description:

This tutorial presents an overview of the ultra-low-power system-level architectures (including sensing technologies, circuits, computing architectures, power management techniques and signal processing applications) for the conception of new wireless body sensor networks (WBSN) products. This tutorial will encompass both lectures and demonstrations of real WBSN working prototypes for human physiological monitoring, and monitoring of healthy life style that outline the challenges of designing, building, and deploying WBSNs in real-life working conditions. The tutorial is organized as a full-day tutorial (6 hours of course in total) with four different parts: 1) Ultra-low-power platforms and system-level architectures for WBSN; 2) Advanced signal processing for biosignals; 3) Power management and energy scavenging; 4) Sensing and interfacing devices for WBSN. The target audience of this tutorial at ASP-DAC includes academic and industrial professionals from fields including EDA, computer and electrical engineering, signal processing, computer science, biomedical engineering and medicine, who are interested in the novel and highly promising field of WBSNs.

Outline:
  • Section 1: "Platforms and System-Level Design of WBSN", Prof. David Atienza
  • Section 2: "Applications and Advanced Signal Processing for Biosignals in WBSN", Dr. Nadia Khaled
  • Section 3: "Energy-driven and event-driven body sensor platforms: when asynchronous systems meets energy harvesting requirements", Dr. Edith Beigné and Dr. Cyril Condemine
  • Section 4: "Sensing devices, applications and design flow for wireless body sensor networks", Dr. Elisabetta Farella

Tutorial 3: Heterogeneity for Power Management: Devices to Systems
Location: Bayside Room 204B

Organizer: Vijaykrishnan Narayanan, The Pennsylvania State University, USA

Speakers:
  • Vijaykrishnan Narayanan (The Pennsylvania State University, USA)
  • Suman Datta (The Pennsylvania State University, USA)
Description:

This tutorial will begin with the introduction of emerging device architectures including high-mobility materials based transistors, multi-gate structures, steep sub-threshold devices and few electron devices that can help to scale supply voltage. Next, we will discuss the implications of such device heterogeneity on system design, especially in enhancing the dynamic range of supply voltage operation. Next, we will focus on how architectural heterogeneity can be employed to enhance power efficiency. We will focus on power optimizations through use of domain-specific accelerators, heterogeneous memory systems and hybrid on-chip networks.

Outline:
  • Section 1: Overview of Power Trends, Challenges and Metrics
  • Section 2: Power-Aware Device Roadmap and Architectural Implications
  • Section 3: Heterogeneous Processor Cores
  • Section 4: Heterogeneous Memory Design
  • Section 5: Heterogeneous On-Chip Networks

Tutorial 4: Energy Efficiency in Scalable Power Sources: Portable to Grid-Connected Systems
Location: Bayside Room 201

Organizer: Naehyuck Chang, Seoul National University, Korea

Speakers:
  • Ittetsu Taniguchi (Ritsumeikan University, Japan)
  • Masahiro Fukui (Ritsumeikan University, Japan)
  • Naehyuck Chang (Seoul National University, Korea)
Description:

Power efficiency is one of the most important design goals in a system ranging from portable applications for longer battery life to Grid-scale applications to go green. Traditionally, power efficiency has been dealt with minimization of power consumption of consumers such as power saving from microprocessors, memory devices, communication interface, display systems, and so forth. However, power efficiency in providers such as Grid, batteries, renewable power sources, fuel cells, power converters, etc., significantly impact on the whole system energy efficiency.

This tutorial emphasizes the importance of the power sources for portable to grid-connected systems. This tutorial consists of three parts: smart Grid design and optimization, battery modeling, and hybrid electrical energy storage systems.

In fact, electronics design automation (EDA) has profound systematic modeling, design, optimization, verification methodologies. Most importantly, system-level design quality will completely differentiate the whole power system performance. Power Grid, battery and energy storage have led by mostly non-EDA research groups. We hope this tutorial will help EDA research groups expand their interest and contribute to energy efficiency optimization of scalable power sources.

For further detailed information of the topics, please click here.

Outline:
  • Topic 1: Smart Grid System Design and Its Optimization - From a Point of View of System Level Design
  • Topic 2: Survey of Battery Modeling and Simulation
  • Topic 3: Hybrid Electrical Energy Storage (HEES) Systems

Tutorial 5: Assertion-based verification for SoC and embedded software
Location: Bayside Room 107

Organizer: Masahiro Fujita, University of Tokyo, Japan

Speakers:
  • Franco Fummi (University of Verona, Italy)
  • Graziano Pravadelli (University of Verona, Italy)
  • Giuseppe Di Gugliemo (University of Verona, Italy)
  • Masahiro Fujita (University of Tokyo, Japan)
Description:

In order to guarantee the correctness of the entire systems to be designs, there must be systematic ways to verify both hardware and software parts of the systems. Assertion based verification (ABV) is a promising approach as it can deal with very large and complicated designs and becoming more and more common for SoC as well as embedded software verification. In this tutorial, current status and future directions on ABV are reviewed and discussed.

In the first part of the tutorial (two hours), basic and advanced ABV methods based on static and dynamic analysis targeting hardware designs including SoC are presented. This covers how to specify assertions, As it is crucial to have sufficient sets of assertions for more complete verification, automatic generation of assertions from simulation results are also presented. It may be time consuming for designers to come up with sufficiently many assertions. Automatic generation of assertions can be very rich and compensate the missing assertions. Both algorithmic as well as empirical results are shown.

In the second part of the tutorial (four hours), dynamic ABV methods for embedded software using model-driven designs are presented. ABV methodologies and tools cannot be applied to hardware and software parts in the same way. Although both static ABV and dynamic ABV methods are widely used for hardware parts, software parts are traditionally verified by means of static ABV methods. This is because dynamic approaches need simulation assumptions that could not be true during execution of general embedded software and also cannot be controlled by the assertion language. Here dynamic ABV methods which exploit model-driven designs for guaranteeing such simulation assumptions are introduced. Then, an ABV framework and tools for embedded software, which automatically synthesizes assertion checkers to verify the embedded software accordingly to the simulation assumptions, is presented.

This tutorial covers practical aspects of system verification and is targeting people who are working on hardware or software verification as well as designers/developers. It is a good introduction to researchers who have interest in the advanced assertion based verification. The tutorial also gives practical aspects of ABV methods including various empirical results by which managing people in SoC and/or embedded software developments can understand the current status and future directions.


Tutorial Pricing

Type

Price

Earlybird Price

Full Registration

$550

$500

IEEE/ACM Member Registration

$475

$425

Student Registration

$340

$290
Last Updated on: 16 January 2012