Title | A Separation and Minimum Wire Length Constrained Maze Routing Algorithm under Nanometer Wiring Rules |
Author | *Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak (National Tsing Hua Univ., Taiwan), Sheng-Hsiung Chen (Springsoft, Taiwan) |
Page | pp. 175 - 180 |
Detailed information (abstract, keywords, etc) | |
Slides |
Title | An ILP-based Automatic Bus Planner for Dense PCBs |
Author | Pei-Ci Wu (Univ. of Illinois, Urbana-Champaign, U.S.A.), Qiang Ma (Synopsys, Inc., U.S.A.), *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 181 - 186 |
Detailed information (abstract, keywords, etc) |
Title | Layer Minimization in Escape Routing for Staggered-Pin-Array PCBs |
Author | *Yuan-Kai Ho, Xin-Wei Shih, Yao-Wen Chang (National Taiwan Univ., Taiwan), Chung-Kuan Cheng (Univ. of California, San Diego, U.S.A.) |
Page | pp. 187 - 192 |
Detailed information (abstract, keywords, etc) |
Title | Network Flow Modeling for Escape Routing on Staggered Pin Arrays |
Author | Pei-Ci Wu, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) |
Page | pp. 193 - 198 |
Detailed information (abstract, keywords, etc) |