| Title | Range and Bitmask Analysis for Hardware Optimization in High-Level Synthesis |
| Author | *Marcel Gort, Jason H. Anderson (Univ. of Toronto, Canada) |
| Page | pp. 773 - 779 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | A Gradual Scheduling Framework for Problem Size Reduction and Cross Basic Block Parallelism Exploitation in High-level Synthesis |
| Author | *Hongbin Zheng, Qingrui Liu, Junyi Li, Dihu Chen, Zixin Wang (Sun Yet-sen Univ., China) |
| Page | pp. 780 - 786 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Implementing Microprocessors from Simplified Descriptions |
| Author | *Nikhil A. Patil, Derek Chiou (Univ. of Texas, Austin, U.S.A.) |
| Page | pp. 787 - 793 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |
| Title | Application-Specific Fault-Tolerant Architecture Synthesis for Digital Microfluidic Biochips |
| Author | *Mirela Alistar, Paul Pop, Jan Madsen (Denmark Technical Univ., Denmark) |
| Page | pp. 794 - 800 |
| Detailed information (abstract, keywords, etc) | |
| Slides | |