| Title | Prefetching Techniques for STT-RAM Based Last-Level Cache in CMP Systems |
| Author | Mengjie Mao (University of Pittsburgh, U.S.A.), Guangyu Sun (Peking University, China), Yong Li, Alex K. Jones, *Yiran Chen (University of Pittsburgh, U.S.A.) |
| Page | pp. 67 - 72 |
| Keyword | prefetch, STT-RAM, last-level cache |
| Abstract | Prefetching is widely used in modern computer systems to mitigate the impact of long memory access latency by paying extra cost in memory and cache accesses. However, the efficacy of prefetching significantly degrades in the memory hierarchy using the emerging spin-transfer torque random access memory (STT-RAM) as last-level cache (LLC) due to the long write access latency. In this work, we propose two orthogonal but complimentary techniques to improve the prefetching efficacy of STT-RAM based LLC in chip multi-processor systems, namely, request prioritization (RP) and hybrid local-global prefetch control (HLGPC). Simulation results show that by combining these two techniques, we can achieve 6.5%~11% system performance improvement and 4.8%~7.3% LLC energy reduction in a quadcore system
with 2MB~8MB STT-RAM based LLC, compared to baseline with basic prefetching. |
| Slides |
| Title | CNPUF: A Carbon Nanotube-based Physically Unclonable Function for Secure Low-Energy Hardware Design |
| Author | *Sven Tenzing Choden Konigsmark, Leslie K. Hwang, Deming Chen, Martin D. F. Wong (University of Illinois at Urbana-Champaign, U.S.A.) |
| Page | pp. 73 - 78 |
| Keyword | PUF, CNT, Low power, Security, Emerging Technology |
| Abstract | Physically Unclonable Functions (PUFs) are used to provide identification, authentication and secret key generation based on unique and unpredictable physical characteristics. Carbon Nanotube Field Effect Transistors (CNFETs) were shown to have excellent electrical and unique physical characteristics and are promising candidates to replace silicon transistors in future Very Large Scale Integration (VLSI) designs. We present Carbon Nanotube PUF (CNPUF), the first PUF design that takes advantage of unique CNFET characteristics. We achieve higher reliability against environmental variations and increased resistance against modeling attacks. Furthermore, we have a considerable power and energy reduction in comparison to previous ultra-low power PUF designs of 89.6% and 98%, respectively. Additionally, CNPUF allows power-security tradeoff. |
| Slides |
| Title | 3DCoB: A New Design Approach for Monolithic 3D Integrated Circuits |
| Author | *Hossam Sarhan, Sebastien Thuries, Olivier Billoint, Fabien Clermidy (CEA-LETI, France) |
| Page | pp. 79 - 84 |
| Keyword | 3D-IC, Monolithic, Sequential Integration, cell-on-cell, cell-on-buffer |
| Abstract | 3D Monolithic Integration (3DMI) technology
provides very high dense vertical interconnects with low
parasitics. Previous 3DMI design approaches provide either
cell-on-cell or transistor-on-transistor integration. In this paper
we present 3D Cell-on-Buffer (3DCoB) as a novel design
approach for 3DMI. Our approach provides a fully compatible
sign-off physical implementation flow with the conventional 2D
tools. We implement our approach on some benchmark circuits
using 28nm-FDSOI technology. The sign-off performance
results show 35% improvement compared to the same 2D
design. |
| Slides |
| Title | Emulator-Oriented Tiny Processors for Unreliable Post-Silicon Devices: A Case Study |
| Author | *Yuko Hara-Azumi (Nara Institute of Science and Technology/JST, PRESTO, Japan), Masaya Kunimoto, Yasuhiko Nakashima (Nara Institute of Science and Technology, Japan) |
| Page | pp. 85 - 90 |
| Keyword | Emulator-oriented processor, Reliability, Post-silicon |
| Abstract | Although various post-silicon devices have been invested in recent years, they still have a major issue of reliability. Because circuit area is an essential factor of reliability, especially for such unreliable post-silicon devices, it is desired to build small circuits which can reuse as many today's application programs as possible even if the performance is not very high. This paper presents the very first work to study novel, efficient techniques of emulating wider-bit guest processors (e.g., 32-bit) on a narrower-bit host processor (e.g., 8-bit) with the very limited hardware resources while mitigating performance degradation. We propose three types of tiny emulation-oriented processors varying in available hardware resources and reliability enhancement approaches. Quantitative evaluation and discussions are done for comparing those three processors. We believe that this work will lead not only acceleration of developing post-silicon technology but also a big paradigm shift in building digital devices. |