| Title | Flexible Packed Stencil Design with Multiple Shaping Apertures for E-Beam Lithography |
| Author | Chris Chu (Iowa State University, U.S.A.), *Wai-Kei Mak (National Tsing Hua University, Taiwan) |
| Page | pp. 137 - 142 |
| Keyword | Electron-beam direct write lithography, Character projection, Stencil design |
| Abstract | Electron-beam direct write (EBDW) lithography is
a promising solution for chip production in the sub-22nm regime.
To improve the throughput of EBDWlithography, character projection
method is commonly employed and a critical problem is to
pack as many characters as possible onto the stencil. In this paper,
we consider two enhancements in packed stencil design over
previous works. First, the use of multiple shaping apertures with
different sizes is explored. Second, the fact that the pattern of a
character can be located anywhere within its enclosing projection
region is exploited to facilitate flexible blank space sharing. For
this packed stencil design problem with multiple shaping apertures
and flexible blank space sharing, a dynamic programming
based algorithm is proposed. Experimental results show that the
proposed enhancement and the associated algorithm can significantly
reduce the total shot count and hence improve the throughput
of EBDW lithography. |
| Slides |
| Title | Self-Aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography |
| Author | Jhih-Rong Gao, Bei Yu, *David Z. Pan (University of Texas at Austin, U.S.A.) |
| Page | pp. 143 - 148 |
| Keyword | SADP, E-Beam, layout decomposition, double patterning |
| Abstract | Advanced lithography techniques enable higher pattern resolution; however, techniques such as extreme ultraviolet lithography and e-beam lithography (EBL) are not yet ready for high volume production. Recently, complementary lithography has be- come promising, which allows two different lithography processes work together to achieve high quality layout patterns while not increasing much manufacturing cost. In this paper, we present a new layout decomposition framework for self-aligned double patterning and complementary EBL, which considers overlay minimization and EBL throughput optimization simultaneously. We perform conflict elimination by merge- and-cut technique and formulate it as a matching- based problem. The results show that our approach is fast and effective, where all conflicts are solved with minimal overlay error and e-beam utilization. |
| Slides |
| Title | Fixing Double Patterning Violations with Look-Ahead |
| Author | *Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H Batterywala (Synopsys India Pvt. Ltd., India) |
| Page | pp. 149 - 154 |
| Keyword | DPT, DRC, lithography, linear program |
| Abstract | Double Patterning Technology (DPT) conflicts express
themselves as odd cycles of spacing between layout shapes. One way of
resolving these is by imposing a large spacing constraint between a pair of shapes participant in an odd cycle. However, this may shrink spacing in other parts of the layout and introduce DRC violations or new DPT conflicts. In this work, we model DPT conflict resolution as a constrained linear optimization problem, look ahead to upfront estimate potential violations and preclude them with additional constraints. We borrow the approach of Satisfiability Modulo Theory (SMT) solvers to simultaneously check satisfiability of linear constraint set and resolution of DPT conflicts. These two are interleaved and feed information to each other to churn out a
feasible set of constraints that fixes DPT and DRC violations. We demonstrate the efficacy of the method on layouts at advanced nodes. |
| Slides |
| Title | EUV-CDA: Pattern Shift Aware Critical Density Analysis for EUV Mask Layouts |
| Author | *Abde Ali Kagalwalla (University of California, Los Angeles, U.S.A.), Michael Lam, Kostas Adam (Mentor Graphics, U.S.A.), Puneet Gupta (University of California, Los Angeles, U.S.A.) |
| Page | pp. 155 - 160 |
| Keyword | EUV, Mask, Yield, DFM, Defect |
| Abstract | Despite the use of mask defect avoidance and mitigation techniques, finding a usable defective mask blank remains a challenge for EUVL at sub-10nm node due to dense layouts and low CD tolerance. In this work, we propose a pattern shift-aware metric called critical density, which can quickly evaluate the robustness of EUV layouts to mask defects (300-1300X faster than naïve Monte Carlo), thereby enabling design-level mask defect mitigation techniques. Our experimental results indicate that regularity hurts layout robustness to mask defects. |
| Slides |