Title | PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices |
Author | *Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta (Univ. of California, Los Angeles, U.S.A.) |
Page | pp. 818 - 824 |
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Title | Modeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture |
Author | *Cong Xu, Dimin Niu (Pennsylvania State Univ., U.S.A.), Shimeng Yu (Arizona State Univ., U.S.A.), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.) |
Page | pp. 825 - 830 |
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Title | The Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design |
Author | Miao Hu (Univ. of Pittsburgh, U.S.A.), Yu Wang (Tsinghua Univ., China), Qinru Qiu (Syracuse Univ., U.S.A.), Yiran Chen, *Hai Li (Univ. of Pittsburgh, U.S.A.) |
Page | pp. 831 - 836 |
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Slides |
Title | Through-Silicon-Via Inductor: Is It Real or Just A Fantasy? |
Author | *Umamaheswara Rao Tida (Missouri Univ. of Science and Tech., U.S.A.), Cheng Zhuo (Intel Research, U.S.A.), Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.) |
Page | pp. 837 - 842 |
Detailed information (abstract, keywords, etc) | |
Slides |