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The 19th Asia and South Pacific Design Automation Conference

Session 9B  Modeling and Evaluator for Emerging Technologies
Time: 15:50 - 17:30 Thursday, January 23, 2014
Location: Room 301
Chairs: Guangyu Sun (Peking Univ., China), Wei Zhang (Hong Kong Univ. of Science and Tech., Hong Kong)

9B-1 (Time: 15:50 - 16:15)
TitlePROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
Author*Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta (Univ. of California, Los Angeles, U.S.A.)
Pagepp. 818 - 824
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9B-2 (Time: 16:15 - 16:40)
TitleModeling and Design Analysis of 3D Vertical Resistive Memory - A Low Cost Cross-Point Architecture
Author*Cong Xu, Dimin Niu (Pennsylvania State Univ., U.S.A.), Shimeng Yu (Arizona State Univ., U.S.A.), Yuan Xie (AMD, China/Pennsylvania State Univ., U.S.A.)
Pagepp. 825 - 830
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9B-3 (Time: 16:40 - 17:05)
TitleThe Stochastic Modeling of TiO2 Memristor and Its Usage in Neuromorphic System Design
AuthorMiao Hu (Univ. of Pittsburgh, U.S.A.), Yu Wang (Tsinghua Univ., China), Qinru Qiu (Syracuse Univ., U.S.A.), Yiran Chen, *Hai Li (Univ. of Pittsburgh, U.S.A.)
Pagepp. 831 - 836
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9B-4 (Time: 17:05 - 17:30)
TitleThrough-Silicon-Via Inductor: Is It Real or Just A Fantasy?
Author*Umamaheswara Rao Tida (Missouri Univ. of Science and Tech., U.S.A.), Cheng Zhuo (Intel Research, U.S.A.), Yiyu Shi (Missouri Univ. of Science and Tech., U.S.A.)
Pagepp. 837 - 842
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