The 20th Asia and South Pacific Design Automation Conference
Technical Program

Remark: The presenter of each paper is marked with "*".

Technical Program: SIMPLE version DETAILED version with abstract One Page (Not Separated) version

Author Index: HERE

Session Schedule

Tuesday, January 20, 2015

Room 103	Room 102	Room 104	Room 105
1K (International Conference Room) Opening & Keynote I 8:30 - 9:50
1S University Design Contest 10:20 - 12:10	1A NoCS I (Performance and Fault Tolerance) 10:20 - 12:00	1B Toward Power Efficient Design 10:20 - 12:00	1C Modeling and Design Methodologies of Post-silicon Devices 10:20 - 12:00
2S (Special Session) Internet of Things 13:50 - 15:30	2A NoCS II (Power and Emerging Technology) 13:50 - 15:30	2B Design Automation for Tomorrow’s Circuit Technologies 13:50 - 15:30	2C Emerging Applications 13:50 - 15:30
3S (Special Session) New Challenges and Solutions in Nanometer Physical Design 15:50 - 17:30	3A Circuits for Performance and Reliability 15:50 - 16:40	3B Frontiers in Logic Synthesis 15:50 - 17:30	3C Energy Optimization for Electric Vehicles and Smart Grids 15:50 - 17:30

Wednesday, January 21, 2015

Room 103	Room 102	Room 104	Room 105
2K (International Conference Room) Keynote II 9:00 - 9:50
4S (Special Session) Machine Learning in EDA: Promises and Challenges in Selected Applications 10:15 - 12:20	4A Efficient NVM Management, from Register to Disk 10:15 - 12:20	4B Robust Timing, and P/G Modeling and Design 10:15 - 12:20	4C New Issues in Placement and Routing 10:15 - 12:20
5S (Designers' Forum ) Car Electronics 13:50 - 15:30	5A Optimization and Exploration for Caches 13:50 - 15:30	5B CAD for Analog/RF/Mixed-Signal Design 13:50 - 15:30	5C Next-Generation Clock Network Synthesis 13:50 - 15:30
6S (Designers' Forum) Panel Discussion: Challenges in the Era of Big-Data Computing 15:50 - 17:30	6A Optimization Techniques for Non-Volatile Memory based Systems 15:50 - 17:30	6B Test for Higher Quality 15:50 - 17:30	6C Reliability 15:50 - 17:30
Banquet (Convention Hall A) 18:00 - 20:00

Thursday, January 22, 2015

Room 103	Room 102	Room 104	Room 105
3K (International Conference Room) Keynote III 9:00 - 9:50
7S (Special Session) The Future of Emerging ReRAM Technology 10:15 - 12:20	7A Ensuring the Correctness of System Integration 10:15 - 12:20	7B Orchestrating Tasks, Cores, and Communication 10:15 - 12:20	7C Design for Manufacturability 10:15 - 12:20
8S (Designers' Forum) Technology Trend toward 8K Era 13:50 - 15:30	8A Exploring Better Architecture of Your Systems 13:50 - 15:30	8B Circuit-Level Modeling and Simulation 13:50 - 15:30	8C Reliable and Trustworthy Electronics 13:50 - 15:30
9S (Designers' Forum) Panel Discussion: IP Base SoC Design and IP Design Innovation 15:50 - 17:30	9A Power/Thermal Management and Modeling 15:50 - 17:30	9B (Special Session) System-Level Designs and Tools for Multicore Systems 15:50 - 17:30	9C Building Secure Systems 15:50 - 17:30