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The 20th Asia and South Pacific Design Automation Conference

Session 3S  (Special Session) New Challenges and Solutions in Nanometer Physical Design
Time: 15:50 - 17:30 Tuesday, January 20, 2015
Location: Room 103
Chair: Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan)

3S-1 (Time: 15:50 - 16:15)
Title(Invited Paper) An Efficient Linear Time Triple Patterning Solver
AuthorHaitong Tian (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys, U.S.A.), Zigang Xiao, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.)
Pagepp. 208 - 213
Detailed information (abstract, keywords, etc)

3S-2 (Time: 16:15 - 16:40)
Title(Invited Paper) Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs
AuthorTiago Reimann (Univ. Federal do Rio Grande do Sul, Brazil), Cliff C.N. Sze (IBM, U.S.A.), *Ricardo Reis (Univ. Federal do Rio Grande do Sul, Brazil)
Pagepp. 214 - 219
Detailed information (abstract, keywords, etc)
Slides

3S-3 (Time: 16:40 - 17:05)
Title(Invited Paper) Analytical Placement for Rectilinear Blocks
Author*Yasuhiro Takashima (Univ. of Kitakyushu, Japan)
Pagepp. 220 - 225
Detailed information (abstract, keywords, etc)
Slides

3S-4 (Time: 17:05 - 17:30)
Title(Invited Paper) IR to Routing Challenge and Solution for Interposer-Based Design
Author*Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang (MediaTek, Taiwan)
Pagepp. 226 - 230
Detailed information (abstract, keywords, etc)