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The 20th Asia and South Pacific Design Automation Conference

Session 6A  Optimization Techniques for Non-Volatile Memory based Systems
Time: 15:50 - 17:30 Wednesday, January 21, 2015
Location: Room 102
Chairs: Guangyu Sun (Peking Univ., China), Ju Lei (Shandong Univ.)

6A-1 (Time: 15:50 - 16:15)
TitleAn Efficient STT-RAM-Based Register File in GPU Architectures
AuthorXiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, *Yiran Chen (Univ. of Pittsburgh, U.S.A.)
Pagepp. 490 - 495
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6A-2 (Time: 16:15 - 16:40)
TitleA Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories
Author*Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan)
Pagepp. 496 - 501
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6A-3 (Time: 16:40 - 17:05)
TitleMinimizing MLC PCM Write Energy for Free through Profiling-Based State Remapping
Author*Mengying Zhao (City Univ. of Hong Kong, Hong Kong), Yuan Xue, Chengmo Yang (Univ. of Delaware, U.S.A.), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)
Pagepp. 502 - 507
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6A-4 (Time: 17:05 - 17:30)
TitleImproving Performance and Lifetime of DRAM-PCM Hybrid Main Memory through a Proactive Page Allocation Strategy
AuthorHoda Aghaei Khouzani, *Chengmo Yang (Univ. of Delaware, U.S.A.), Jingtong Hu (Oklahoma State Univ., U.S.A.)
Pagepp. 508 - 513
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